Semiconductor memory device and method of formation

• US 5,308,782 A
• Filed: 10/26/1992
• Issued: 05/03/1994
• Est. Priority Date: 03/02/1992
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Witek, Keith E., Mazure, Carlos A., Hayden, James D., Fitch, Jon T.
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US07/966,643
• Time in Patent Office: 554 Days
• Field of Search: 437/47, 437/48, 437/52, 437/60, 437/915, 437/56, 437/57, 437/83, 437/84, 437/89
• US Class Current: 438/154
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical transistor stack (124) is formed. The first vertical transistor stack (122) has a transistor (100) underlying a transistor (104). The second vertical transistor stack (124) has a transistor (102) underlying a transistor (106). The transistors (100 and 104) are connected in series, and the transistors (102 and 106) are connected in series. In a preferred form, transistors (100 and 102) are electrically connected as latch transistors for a semiconductor memory device and transistors (106 and 104) are connected as pass transistors. Two vertical stacks (126 and 128) form electrical interconnections (118 and 120) and resistive devices (134 and 138) for the semiconductor memory device.

Claims

1. A method for forming a semiconductor memory device comprising the steps of:

providing a substrate having a surface;

forming a first transistor at least partially overlying the surface of the substrate, the first transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region between the first and second current electrodes, and at least one gate electrode adjacent the channel region;

forming a second transistor overlying the first transistor, the second transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region between the first and second current electrodes, and at least one gate electrode adjacent the channel region, the second current electrode of the first transistor being coupled to the first current electrode of the second transistor to form a first memory node;

coupling the first memory node to an output conductor wherein the output conductor functions to provide a voltage of the first memory node external to the first and second transistors; and

electrically coupling the first transistor in series with the second transistor wherein a second memory node is formed by the first current electrode of the first transistor and a third memory node is formed by the second current electrode of the second transistor.

2. The method of claim 1 further comprising:

forming a third transistor at least partially overlying the surface of the substrate, the third transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region between the first and second current electrodes, and at least one gate electrode adjacent the channel region;

forming a fourth transistor overlying the third transistor, the fourth transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region between the first and second current electrodes, and at least one gate electrode adjacent the channel region; and

electrically coupling the third transistor to the first memory node.

3. The method of claim 2 wherein both the steps of forming the third and fourth transistors further comprise:

forming both the third and fourth transistors as N-channel transistors.

4. The method of claim 1 wherein both the steps of forming the first and second transistors further comprise:

forming both the first and second transistors as N-channel transistors.

5. The method of claim 1 wherein the step of providing a substrate further comprises:

forming a diffusion region within the substrate, the diffusion region underlying the first transistor.

6. The method of claim 5 wherein the step of forming a diffusion region further comprises:

forming a silicided region adjacent the diffusion region.

7. The method of claim 1 wherein the step of forming the first transistor further comprises:

coupling a current electrode of the first transistor to a resistive device via a conductive interconnection.

8. The method of claim 7 wherein the step of forming the first transistor further comprises:

forming said resistive device as a resistor.

9. The method of claim 7 wherein the step of forming the first transistor further comprises:

forming said resistive device as a P-channel transistor.

10. The method of claim 7 wherein the step of forming the first transistor further comprises:

forming a capacitive element adjacent said conductive interconnection.

11. The method of claim 7 wherein the step of forming the first transistor further comprises:

forming the conductive interconnection directly underlying said resistive device.

12. The method of claim 1 wherein both the steps of forming the first and second transistors further comprise:

epitaxially growing portions of the first and second transistors.

13. The method of claim 1 wherein the step of forming one of either the first transistor or the second transistor further comprises:

forming a gate dielectric for one of either the first transistor or the second transistor as a composite dielectric, the composite dielectric having a first region made of a first dielectric material and a second region made of a second dielectric material.

14. The method of claim 1 wherein the step of electrically coupling comprises:

connecting the second memory node to a ground potential terminal for providing a ground potential; and

using the third memory node as a bit line to provide a binary data bit external to the semiconductor memory device.

15. A method for forming a random access memory structure wherein the method comprises:

forming a first vertical transistor having a first current electrode for conducting a ground potential, a second current electrode overlying the first current electrode, a channel region separating the first current electrode and the second current electrode, and a gate electrode adjacent the channel region;

forming a second vertical transistor overlying the first vertical transistor, the second vertical transistor having a first current electrode coupled to the second current electrode of the first vertical transistor to form a first storage node, a second current electrode overlying the first current electrode of the second transistor, the second current electrode of the second transistor functioning as a first bit line to provide data external to the random access memory structure, a channel region separating the first and second current electrodes, and a gate electrode coupled to a first word line conductor wherein the first word line conductor selectively turns on the second transistor; and

forming a first load device wherein the first load device has a first terminal coupled to the first storage node and a second terminal coupled to a power supply voltage terminal.

16. The method of claim 15 further comprising:

forming a third vertical transistor laterally separated from the first vertical transistor, the third vertical transistor having a first current electrode for conducting the ground potential, a second current electrode, a channel region separating the first current electrode and the second current electrode, and a gate electrode adjacent the channel region;

forming a fourth vertical transistor overlying the third vertical transistor, the fourth vertical transistor having a first current electrode coupled to the second current electrode of the third vertical transistor to form a second storage node, a second current electrode which functions as a second bit line to provide data external to the random access memory structure, a channel region separating the first and second current electrodes, and a gate electrode coupled to a second word line conductor wherein the second word line conductor selectively turns on the fourth vertical transistor; and

forming a second load device wherein the second load device has a first terminal coupled to the second storage node and a second terminal coupled to the power supply voltage terminal.

17. The method of claim 16 further comprising:

electrically coupling the gate electrode of the first vertical transistor to the second storage node; and

electrically coupling the gate electrode of the third vertical transistor to the first storage node.

18. The method of claim 16 wherein the first word line conductor is connected to the second word line conductor to form a single word line conductor.

19. The method of claim 15 wherein the step of forming the first load device comprises:

forming the first load device as a device selected from a group consisting of;

a resistor and a P-channel transistor.

20. A method for forming a random access memory structure wherein the method comprises:

forming a first N-channel vertical transistor having a first current electrode for carrying a ground potential, a second current electrode overlying the first current electrode, a channel region separating the first current electrode and the second current electrode, and a gate electrode adjacent the channel region;

forming a first P-channel vertical transistor overlying the first N-channel vertical transistor, the first P-channel vertical transistor having a first current electrode coupled to the second current electrode of the first N-channel vertical transistor to form a first storage node, a second current electrode overlying the first current electrode of the first N-channel vertical transistor, the second current electrode of the first P-channel vertical transistor being coupled to a power supply voltage terminal, a channel region separating the first and second current electrodes of the first P-channel vertical transistor, and a gate electrode coupled the gate electrode of the first N-channel vertical transistor; and

forming a first N-channel pass transistor wherein the first N-channel pass transistor has a first current electrode coupled to the first storage node, a second current electrode coupled to a first bit line conductor, and a gate electrode coupled to a first word line conductor.

21. The method of claim 20 further comprising:

forming a second N-channel vertical transistor laterally separated from the first N-channel vertical transistor, the second N-channel vertical transistor having a first current electrode for conducting the ground potential, a second current electrode overlying the first current electrode, a channel region separating the first current electrode and the second current electrode, and a gate electrode adjacent the channel region;

forming a second P-channel vertical transistor overlying the second N-channel vertical transistor, the second P-channel vertical transistor having a first current electrode coupled to the second current electrode of the second N-channel vertical transistor to form a second storage node, a second current electrode overlying the first current electrode of the second N-channel vertical transistor, the second current electrode of the second P-channel vertical transistor being coupled to a power supply voltage terminal, a channel region separating the first and second current electrodes, and a gate electrode coupled to the gate electrode of the second N-channel vertical transistor, the gate of the first N-channel vertical transistor being coupled to the second storage node and the gate of the second N-channel vertical transistor being coupled to the first storage node; and

forming a second N-channel pass transistor wherein the second N-channel pass transistor has a first current electrode coupled to the second storage node, a second current electrode coupled to a second bit line conductor, and a gate electrode coupled to a second word line conductor.

22. A method for forming a static random access memory cell wherein the method comprises:

forming a first vertical transistor having a first current electrode for carrying a ground potential, a second current electrode overlying the first current electrode, a channel region separating the first current electrode and the second current electrode, and a gate electrode adjacent the channel region, the first vertical transistor being an N-channel transistor;

forming a second vertical transistor overlying the first vertical transistor, the second vertical transistor having a first current electrode coupled to the second current electrode of the first vertical transistor to form a first storage node, a second current electrode overlying the first current electrode of the second transistor, the second current electrode of the second vertical transistor being coupled to a first bit line to provide data external to the random access memory cell, a channel region separating the first and second current electrodes, and a gate electrode coupled to a word line conductor wherein the first word line conductor selectively makes the second transistor conduct current, the second vertical transistor being an N-channel transistor;

forming a first resistive load device wherein the first resistive load device has a first terminal coupled to the first storage node and a second terminal coupled to a power supply voltage terminal;

forming a third vertical transistor laterally separated from the first vertical transistor, the third vertical transistor having a first current electrode for conducting a ground potential, a second current electrode coupled to the gate electrode of the first vertical transistor, a channel region separating the first current electrode and the second current electrode, and a gate electrode adjacent the channel region which is coupled to the second current electrode of the first vertical transistor, the third vertical transistor being an N-channel transistor;

forming a fourth vertical transistor overlying the third vertical transistor, the fourth vertical transistor having a first current electrode coupled to the second current electrode of the third vertical transistor to form a second storage node, a second current electrode coupled to a second bit line to provide data external to the random access memory cell, a channel region separating the first and second current electrodes, and a gate electrode coupled to the word line conductor wherein the word line conductor selectively makes the fourth vertical transistor conduct current, the fourth vertical transistor being an N-channel transistor; and

forming a second resistive load device wherein the second resistive load device has a first terminal coupled to the second storage node and a second terminal coupled to a power supply voltage terminal.