Data carrier for identification systems

• US 5,308,967 A
• Filed: 06/18/1992
• Issued: 05/03/1994
• Est. Priority Date: 10/26/1990
• Status: Expired due to Term

• Current Assignee: Reinhard Jurisch
• Original Assignee: Reinhard Jurisch
• Inventors: Jurisch, Reinhard
• Primary Examiner(s): Hajec, Donald
• Assistant Examiner(s): FILIPEK, JEFFER
• Application Number:
  US07/861,859
• Time in Patent Office: 684 Days
• Field of Search: 257/922, 257/926, 257/679, 257/531, 235/449, 235/492
• US Class Current: 235/492
• CPC Class Codes: G06K 19/07747 at least one of the integrated circuit chips being mounted as a module
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/0775 arrangements for connecting the integrated circuit to the antenna
• CPC Class Codes: G06K 19/07775 the antenna being on-chip
• CPC Class Codes: G06K 19/07779 the inductive antenna being a coil
• CPC Class Codes: G06K 19/07781 the coil being fabricated in a winding process

Abstract

A data carrier in which all integrated circuits are monolithically integrated in a single chip and at least one non-displaceably connected antenna coil is monolithically provided right upon the active semiconductor areas of the chip upon partial ranges of the uppermost conductive paths.

Claims

1. Data carrier chip for identification systems comprising at least one integrated circuit including active semiconductor areas and uppermost conductive path structures and one coil arrangement connected to said integrated circuit, said coil arrangement being substantially located above the active semiconductor areas of the data carrier chip on sections of the uppermost conductive path structures, the improvement wherein the windings of said coil arrangement include a low-ohmic portion that is exclusively and monolithically provided on the data carrier chip itself with a cross sectional thickness in a direction parallel to the normal of the chip being greater than 5 μ

m, said coil arrangement being aligned with said active semiconductor areas in said direction normal to said coil arrangement.

2. Data carrier chip for identification systems as claimed in claim 1, wherein the material of the low-ohmic portion of the coil arrangement windings is selected from a different material of lower specific resistance than the material of the uppermost conductive path structures.

3. Data carrier chip for identification systems as claimed in claim 1 wherein said coil arrangement includes a first and second coil, said first coil being lower ohmic than said second coil and having an area resistance of ≦

5 m Ω

/□

.

4. Data carrier chip for identification systems as claimed in claim 1, wherein the material of the low-ohmic portion of the coil arrangement windings is substantially gold.

5. Data carrier chip for identification systems as claimed in claim 1, wherein at least the low-ohmic portion of the arrangement windings is manufactured by bump technology electro-plating-process.