Insulated gate field effect semiconductor devices having a LDD region and an anodic oxide film of a gate electrode

• US 5,308,998 A
• Filed: 08/24/1992
• Issued: 05/03/1994
• Est. Priority Date: 08/26/1991
• Status: Expired

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko, Yamazaki, Shunpei, Zhang, Hongyong
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US07/933,810
• Time in Patent Office: 617 Days
• Field of Search: 257/57, 257/63, 257/66, 257/410, 257/411, 257/412, 257/336, 257/344, 257/408, 257/59, 257/64, 257/72, 257/347, 257/350, 257/351, 257/369, 437/42, 437/907
• US Class Current: 257/57
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136245 having complementary transistors
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
• CPC Class Codes: H01L 29/78651 Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

An IGFET has differential crystallinity in offset regions near the source-channel and drain-channel boundaries. In one embodiment, an offset region with crystallinity different from that of an adjacent region is provided between the channel and at least one of the source and drain regions. An oxide film may be provided to cover the surface of the gate electrode, formed by anodizing the surface of the gate electrode, and this layer may be used as a mask when forming the crystallinity offset regions.

Claims

1. An insulated gate field effect semiconductor device comprising:

a first impurity region of a first conductivity type formed within a semiconductor substrate;

a second impurity region of said first conductivity type formed within said semiconductor substrate;

a channel region located between said first and second impurity regions within said semiconductor substrate;

a gate electrode formed over said channel region through a gate insulating layer therebetween, a surface of said gate electrode covered with an anodic oxidation film thereof; and

a third impurity region of said first conductivity type located between said channel region and at least one of said first and second impurity regions formed within said semiconductor substrate,

wherein a crystallinity of said third impurity region is lower than the crystallinity of said first and second impurity regions.

2. The insulated gate field effect semiconductor device as claimed in claim 1 wherein the band-gap of said third impurity region is wider than that of said first and second impurity regions.

3. An insulated gate field effect transistor comprising:

a semiconductor layer formed on a substrate;

source and drain regions formed within said semiconductor layer;

a channel region extending between said source and drain regions within said semiconductor layer;

a gate electrode formed on said channel region through a gate insulating layer therebetween; and

an anodic oxide film of said gate electrode covering a surface of said gate electrode

wherein at least a lightly doped region is formed between said channel and at least one of said source and drain regions.

4. An insulated gate field effect transistor comprising:

source and drain semiconductor regions formed on a substrate;

a channel semiconductor region extending between said source and drain regions on said substrate;

a gate electrode formed on said channel region with a gate insulating layer therebetween, a surface of said gate electrode covered with an anodic oxide film of said gate electrode;

wherein portions of said source and drain regions in the vicinity of said channel region have a lower degree of crystallinity than the other portions of said source and drain regions.

5. An insulated gate field effect transistor comprising:

source and drain semiconductor regions formed on a substrate;

a channel semiconductor region extending between said source and drain regions on said substrate;

a gate electrode formed on said channel region with a gate insulating layer therebetween;

wherein portions of said source and drain regions in the vicinity of said channel region have a lower degree of crystallinity than the other portions of said source and drain regions, and said gate electrode is offset with respect to said source and drain regions in order not to overlap said regions.

6. A semiconductor device comprising first and second insulated gate field effect transistors, each of said transistors comprising source and drain semiconductor regions formed on a substrate, a channel semiconductor region extending between said source and drain regions on said substrate, and a gate electrode formed on said channel region with a gate insulating layer therebetween, wherein portions of said source and drain regions in the vicinity of said channel region have a lower degree of crystallinity than the other portions of said source and drain regions, and said gate electrode is offset by an offset distance with respect to said source and drain regions in order not to overlap said regions,

wherein the offset distance of said first transistor is less than the offset distance of said second transistor.

7. The device of claim 6 wherein said first transistor is a n-channel transistor and said second transistor is a p-channel transistor.

8. A semiconductor device comprising first and second insulated gate field effect transistors, each of said transistors comprising source and drain semiconductor regions formed on a substrate, a channel semiconductor region extending between said source and drain regions on said substrate, a gate electrode formed on said channel region with a gate insulating layer therebetween, and an anodic oxide film formed of a material of said gate electrode and covering a surface of said gate electrode, wherein portions of said source and drain regions in the vicinity of said channel region have a lower degree of crystallinity than the other portions of said source and drain regions,

wherein a thickness of said anodic oxide film of said first transistor is thinner than a thickness of said anodic oxide film of said second transistor.

9. The device of claim 8 wherein said first transistor is an n-channel transistor and said second transistor is a p-channel transistor.

10. A semiconductor device comprising first and second insulated gate field effect transistors, each of said transistors comprising source and drain semiconductor regions formed on a substrate, a channel semiconductor region extending between said source and drain regions on said substrate, and a gate electrode formed on said channel region with a gate insulating layer therebetween, wherein portions of said source and drain regions in the vicinity of said channel region have a lower degree of crystallinity than the other portions of said source and drain regions,

wherein said portions having a lower degree of crystallinity in said first transistor are thinner, in a direction from said source or drain region including said portion to said channel region, than said portions having a lower degree of crystallinity in said second transistor.

11. The device of claim 10 wherein said first transistor is an n-channel transistor and said second transistor is a p-channel transistor.