Semiconductor bond pad structure and method

• US 5,309,025 A
• Filed: 07/27/1992
• Issued: 05/03/1994
• Est. Priority Date: 07/27/1992
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Chen, Fusen E., Bryant, Frank R.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Meier, Stephen D.
• Application Number:
  US07/919,949
• Time in Patent Office: 645 Days
• Field of Search: 257/784, 257/774, 257/751, 257/780, 257/915
• US Class Current: 257/784
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05082 Two-layer arrangements
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05188
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A method for forming an improved bonding pad structure. A bond pad structure is formed by depositing a barrier layer over an underlying region of a semiconductor device, and then depositing a first conductive layer over the barrier layer. The barrier layer and conductive layer are then patterned and etched to define a conductive region. In a preferred embodiment, the conductive region is formed in the shape of a grid. A second conductive layer is deposited over the conductive region and a portion of the exposed underlying region. The second conductive layer makes a good adhesive contact with the underlying region, thus preventing bond pad lift off.

Claims

1. A bond pad structure in an integrated circuit, comprising:

a semiconductor device having an underlying region;

at least one barrier layer deposited over the underlying region, wherein a portion of the underlying region is exposed;

a first conductive layer deposited over the at least one barrier layer to form a conductive region, wherein the exposed portion of the underlying region remains exposed; and

a second conductive layer deposited over the first conductive layer and the exposed portion of the underlying region.

2. The bond pad structure according to claim 1, wherein the underlying region is oxide.

3. The bond pad structure according to claim 1, further comprising insulating sidewall regions surrounding the conductive region.

4. The bond pad structure according to claim 3, wherein the sidewall regions are comprised of oxide.

5. The bond pad structure according to claim 1, wherein the conductive region forms the shape of a grid.

6. The bond pad structure according to claim 1, wherein the conductive region forms the shape of a polygon.

7. The bond pad structure according to claim 1, wherein the conductive region forms the shape of a ring.

8. The bond pad structure according to claim 1, wherein the barrier layer is comprised of titanium nitride.

9. The bond pad structure according to claim 1, wherein the first conductive layer is comprised of metal.

10. The bond pad structure according to claim 9, wherein the metal is aluminum.

11. A bond pad structure in an integrated circuit, comprising:

a semiconductor device having an underlying region, wherein the underlying region is oxide;

a conductive region deposited over the semiconductor device; and

at least one barrier region, wherein a portion of the conductive region is in direct contact with the underlying region and a portion of the conductive region is not in direct contact with the underlying region, further wherein the portion of the conductive region not in direct contact with the underlying region is separated from the underlying region by the barrier region.

12. A bond pad structure in an integrated circuit, comprising:

a semiconductor device having an underlying region;

a conductive region deposited over the semiconductor device; and

at least one barrier region, wherein a portion of the conductive region is in direct contact with the underlying region and a portion of the conductive region is not in direct contact with the underlying region, further wherein the portion of the conductive region not in direct contact with the underlying region is separated from the underlying region by the barrier region, wherein the barrier layer is titanium nitride.