Power supply dependent input buffer
First Claim
1. A power supply dependent input buffer, comprising:
- differential amplifier means for receiving an ECL level signal referenced to a first power supply voltage, and in response, providing first and second differential signals;
an emitter-follower circuit, coupled to said differential amplifier, for receiving said first differential signal, and in response, providing a first level shifted signal;
a first resistor, coupled to said emitter-follower circuit, for receiving said first level shifted signal, and in response, providing a second level shifted buffered signal, said second level shifted buffered signal referenced to a second power supply voltage; and
current source means, coupled to said first resistor, for receiving a bias voltage, said bias voltage referenced to said first power supply voltage, said current source means providing a current for said first resistor, said current being proportional to said first power supply voltage.
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Accused Products
Abstract
A power supply dependent input buffer (20) having a differential amplifier (22), emitter-follower transistors (29 and 32), level shifting resistors (30 and 33), and power supply dependent current sources (31 and 34) receives an ECL input signal referenced to a positive power supply voltage and provides buffered level shifted signals referenced to ground. The current sources (31 and 34) receive a power supply dependent bias voltage that changes in relation to a change in the positive power supply voltage. In turn, the voltage drop across the resistors (30 and 33) changes with respect to the positive power supply voltage such that the buffered level shifted signals are constant with respect to ground. The power supply dependent input buffer (20) is for use at low power supply voltages (such as 3.3 volts), resulting in low power consumption and wider margins on following stages, such as a level converter.
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Citations
13 Claims
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1. A power supply dependent input buffer, comprising:
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differential amplifier means for receiving an ECL level signal referenced to a first power supply voltage, and in response, providing first and second differential signals; an emitter-follower circuit, coupled to said differential amplifier, for receiving said first differential signal, and in response, providing a first level shifted signal; a first resistor, coupled to said emitter-follower circuit, for receiving said first level shifted signal, and in response, providing a second level shifted buffered signal, said second level shifted buffered signal referenced to a second power supply voltage; and current source means, coupled to said first resistor, for receiving a bias voltage, said bias voltage referenced to said first power supply voltage, said current source means providing a current for said first resistor, said current being proportional to said first power supply voltage. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A power supply dependent input buffer, comprising:
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differential amplifier means for receiving an ECL level signal referenced to a first power supply voltage, and in response, providing first and second differential signals; a first emitter-follower circuit, coupled to said differential amplifier, for receiving said first differential signal, and in response, providing a first level shifted differential signal; a second emitter-follower circuit, coupled to said differential amplifier, for receiving said second differential signal, and in response, providing a second level shifted differential signal; a first resistor having a first terminal coupled to said first emitter-follower circuit for receiving said first level shifted differential signal, and a second terminal; a second resistor, having a first terminal coupled to said second emitter-follower circuit for receiving said second level shifted differential signal, and a second terminal; current source means, coupled between said second terminals of each of said first and second resistors and a second power supply voltage terminal, for receiving a power supply dependent bias voltage, said power supply dependent bias voltage referenced to said first power supply voltage, said current source means for providing a current for said first and second resistors proportional to said first power supply voltage; and wherein said first resistor is for providing a third level shifted buffered signal, said third level shifted buffered signal referenced to a second power supply voltage, and said second resistor is for providing a fourth level shifted buffered signal, said fourth level shifted buffered signal referenced to said second power supply voltage. - View Dependent Claims (8, 9, 10, 11)
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12. A power supply dependent input buffer, comprising:
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a differential amplifier, including first and second resistors and first and second bipolar transistors, for receiving a first input signal, said first input signal being referenced to a positive power supply voltage, and in response, said differential amplifier providing first and second differential signals; a first emitter-follower transistor having a first current electrode coupled to a positive power supply voltage terminal, a control electrode coupled to a first current electrode of said first bipolar transistor, and a second current electrode; a second emitter-follower transistor having a first current electrode coupled to a positive power supply voltage terminal, a control electrode coupled to a first current electrode of said second bipolar transistor, and a second current electrode; a third resistor having a first terminal coupled to said second current electrode of said first emitter-follower transistor, and a second terminal for providing a first buffered signal, said first buffered signal being referenced to a negative power supply voltage; a fourth resistor having a first terminal coupled to said second current electrode of said second emitter-follower transistor, and a second terminal for providing a second buffered signal, said second buffered signal being referenced to said negative power supply voltage; a first N-channel transistor, having a drain coupled to said second terminal of said third resistor, a gate for receiving a power supply dependent bias voltage, and a source coupled to a negative power supply voltage terminal; and a second N-channel transistor, having a drain coupled to said second terminal of said fourth resistor, a gate for receiving said power supply dependent bias voltage, and a source coupled to said negative power supply voltage terminal. - View Dependent Claims (13)
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Specification