Power supply dependent input buffer

• US 5,309,039 A
• Filed: 09/29/1992
• Issued: 05/03/1994
• Est. Priority Date: 09/29/1992
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Pelley, Perry H. III, Ghassemi, Hamed
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): PHAN, TRONG Q
• Application Number:
  US07/953,153
• Time in Patent Office: 581 Days
• Field of Search: 307/570, 307/446, 307/296.6, 307/296.1, 307/296.7, 307/494
• US Class Current: 327/542
• CPC Class Codes: H03K 19/00376 in bipolar transistor circuits
• CPC Class Codes: H03K 19/017527 with at least one differential stage

Abstract

A power supply dependent input buffer (20) having a differential amplifier (22), emitter-follower transistors (29 and 32), level shifting resistors (30 and 33), and power supply dependent current sources (31 and 34) receives an ECL input signal referenced to a positive power supply voltage and provides buffered level shifted signals referenced to ground. The current sources (31 and 34) receive a power supply dependent bias voltage that changes in relation to a change in the positive power supply voltage. In turn, the voltage drop across the resistors (30 and 33) changes with respect to the positive power supply voltage such that the buffered level shifted signals are constant with respect to ground. The power supply dependent input buffer (20) is for use at low power supply voltages (such as 3.3 volts), resulting in low power consumption and wider margins on following stages, such as a level converter.

Claims

1. A power supply dependent input buffer, comprising:

differential amplifier means for receiving an ECL level signal referenced to a first power supply voltage, and in response, providing first and second differential signals;

an emitter-follower circuit, coupled to said differential amplifier, for receiving said first differential signal, and in response, providing a first level shifted signal;

a first resistor, coupled to said emitter-follower circuit, for receiving said first level shifted signal, and in response, providing a second level shifted buffered signal, said second level shifted buffered signal referenced to a second power supply voltage; and

current source means, coupled to said first resistor, for receiving a bias voltage, said bias voltage referenced to said first power supply voltage, said current source means providing a current for said first resistor, said current being proportional to said first power supply voltage.

2. The power supply dependent input buffer of claim 1, wherein said first power supply voltage is characterized as being a positive power supply voltage, and said second power supply voltage is characterized as being ground.

3. The power supply dependent input buffer of claim 1, wherein said bias voltage is provided by a power supply dependent bias voltage generator, comprising:

a first resistor having a first terminal coupled to a first power supply voltage terminal for receiving said first power supply voltage, and a second terminal;

an amplifier, including first and second load elements and first and second transistors, a control electrode of said first transistor coupled to said second terminal of said first resistor of said power supply dependent bias voltage generator;

a second resistor having a first terminal coupled to a control electrode of said second transistor, and having a second terminal for receiving a reference voltage, and in response to receiving said reference voltage, said second resistor providing a first current;

a current mirror, coupled to said amplifier and to said second resistor, for receiving said first current and for generating a second current proportional to said first current; and

a third transistor having a first current electrode and a first control electrode coupled to said current mirror for providing said power supply dependent bias voltage, and a second control electrode coupled to a second power supply voltage terminal for receiving said second power supply voltage.

4. The power supply dependent input buffer of claim 3, wherein said first and second load elements are P-channel transistors.

5. The power supply dependent input buffer of claim 3, wherein said reference voltage is characterized as being a bandgap generated reference voltage.

6. The power supply dependent input buffer of claim 1, wherein said current source means comprises a first N-channel transistor having a drain coupled to said first resistor, a gate for receiving said power supply dependent bias voltage, and a source coupled to said second power supply voltage terminal.

7. A power supply dependent input buffer, comprising:

differential amplifier means for receiving an ECL level signal referenced to a first power supply voltage, and in response, providing first and second differential signals;

a first emitter-follower circuit, coupled to said differential amplifier, for receiving said first differential signal, and in response, providing a first level shifted differential signal;

a second emitter-follower circuit, coupled to said differential amplifier, for receiving said second differential signal, and in response, providing a second level shifted differential signal;

a first resistor having a first terminal coupled to said first emitter-follower circuit for receiving said first level shifted differential signal, and a second terminal;

a second resistor, having a first terminal coupled to said second emitter-follower circuit for receiving said second level shifted differential signal, and a second terminal;

current source means, coupled between said second terminals of each of said first and second resistors and a second power supply voltage terminal, for receiving a power supply dependent bias voltage, said power supply dependent bias voltage referenced to said first power supply voltage, said current source means for providing a current for said first and second resistors proportional to said first power supply voltage; and

wherein said first resistor is for providing a third level shifted buffered signal, said third level shifted buffered signal referenced to a second power supply voltage, and said second resistor is for providing a fourth level shifted buffered signal, said fourth level shifted buffered signal referenced to said second power supply voltage.

8. The power supply dependent input buffer of claim 7, wherein said first power supply voltage is characterized as being a positive power supply voltage, and said second power supply voltage is characterized as being ground.

9. The power supply dependent input buffer of claim 7, wherein said current source means comprises:

a first N-channel transistor having a drain coupled to said second terminal of said first resistor, a gate for receiving said power supply dependent bias voltage, and a source coupled to a second power supply voltage terminal for receiving said second power supply voltage; and

a second N-channel transistor having a drain coupled to said second terminal of said second resistor, a gate for receiving said power supply dependent bias voltage, and a source coupled to said second power supply voltage terminal for receiving said second power supply voltage.

10. The power supply dependent input buffer of claim 7, wherein said bias voltage is provided by a power supply dependent bias voltage generator, comprising:

a first resistor having a first terminal coupled to a first power supply voltage terminal, and a second terminal;

an amplifier, including first and second load elements and first and second transistors, a control electrode of said first transistor coupled to said second terminal of said first resistor of said power supply dependent bias voltage generator;

a second resistor having a first terminal coupled to a control electrode of said second transistor, and having a second terminal for receiving a reference voltage, and in response to receiving said reference voltage, said second resistor providing a first current;

a current mirror, coupled to said amplifier and to said second resistor, for receiving said first current and for generating a second current proportional to said first current; and

a third transistor having a first current electrode and a first control electrode coupled to said current mirror for providing said power supply dependent bias voltage, and a second current electrode coupled to a second power supply voltage terminal.

11. The power supply dependent input buffer of claim 10, wherein said reference voltage is characterized as being a bandgap generated reference voltage.

12. A power supply dependent input buffer, comprising:

a differential amplifier, including first and second resistors and first and second bipolar transistors, for receiving a first input signal, said first input signal being referenced to a positive power supply voltage, and in response, said differential amplifier providing first and second differential signals;

a first emitter-follower transistor having a first current electrode coupled to a positive power supply voltage terminal, a control electrode coupled to a first current electrode of said first bipolar transistor, and a second current electrode;

a second emitter-follower transistor having a first current electrode coupled to a positive power supply voltage terminal, a control electrode coupled to a first current electrode of said second bipolar transistor, and a second current electrode;

a third resistor having a first terminal coupled to said second current electrode of said first emitter-follower transistor, and a second terminal for providing a first buffered signal, said first buffered signal being referenced to a negative power supply voltage;

a fourth resistor having a first terminal coupled to said second current electrode of said second emitter-follower transistor, and a second terminal for providing a second buffered signal, said second buffered signal being referenced to said negative power supply voltage;

a first N-channel transistor, having a drain coupled to said second terminal of said third resistor, a gate for receiving a power supply dependent bias voltage, and a source coupled to a negative power supply voltage terminal; and

a second N-channel transistor, having a drain coupled to said second terminal of said fourth resistor, a gate for receiving said power supply dependent bias voltage, and a source coupled to said negative power supply voltage terminal.

13. The power supply dependent input buffer of claim 12, wherein said power supply dependent bias voltage is provided by a power supply dependent bias voltage generator, comprising:

a first resistor having a first terminal coupled to said positive power supply voltage terminal, and a second terminal;

a first N-channel transistor having a drain coupled to said second terminal of said first resistor of said power supply voltage generator, a gate for receiving a second bias voltage, and a source coupled to said negative power supply voltage terminal;

a first bipolar transistor having a collector coupled to said positive power supply voltage terminal, a base coupled to said second terminal of said first resistor of said power supply voltage generator, and an emitter;

a second N-channel transistor having a drain coupled to said emitter of said first bipolar transistor of said power supply voltage generator, a gate for receiving said power supply dependent bias voltage, and a source coupled to said negative power supply voltage terminal;

a first P-channel transistor having a source coupled to said positive power supply voltage terminal, a gate, and a drain;

a second P-channel transistor having a source coupled to said positive power supply voltage terminal, and a gate and a drain both coupled to said gate of said first P-channel transistor;

a second bipolar transistor having a collector coupled to said drain of said first P-channel transistor, a base coupled to said emitter of said first bipolar transistor of said power supply voltage generator, and an emitter;

a third bipolar transistor having a collector coupled to said drain of said second P-channel transistor, a base, and an emitter coupled to said emitter of said second bipolar transistor of said power supply voltage generator;

a third P-channel transistor having a source coupled to said positive power supply voltage terminal, a gate coupled to said drain of said first P-channel transistor, and a drain coupled to said base of said third bipolar transistor of said power supply voltage generator;

a second resistor having a first terminal coupled to said drain of said third P-channel transistor, and a second terminal for receiving a bandgap generated reference voltage;

a fourth P-channel transistor having a source coupled to said positive power supply voltage terminal, a gate coupled to said drain of said first P-channel transistor, and a drain; and

a third N-channel transistor having a drain and a gate both coupled to said drain of said fourth P-channel transistor for providing said power supply dependent bias voltage, and a source coupled to said negative power supply voltage terminal.