Method of and apparatus for designing circuit block layout in integrated circuit

• US 5,309,371 A
• Filed: 06/26/1990
• Issued: 05/03/1994
• Est. Priority Date: 06/28/1989
• Status: Expired due to Term

• Current Assignee: Kawasaki MicroElectronics (Megachips Corporation)
• Original Assignee: Kawasaki Steel Corporation (JFE Holdings Incorporated)
• Inventors: Moriya, Shoichi, Seki, Naoyasu, Muraishi, Yoshito, Shikata, Hiromi
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US07/543,549
• Time in Patent Office: 1,407 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/121
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

There are provided a method of and an apparatus for designing a circuit block layout in an integrated circuit wherein minimization of a total wiring length among the circuit blocks and compaction of the circuit blocks are automatically achieved upon automatically laying out the circuit blocks and determining wiring among those circuit blocks, by initially laying out the circuit blocks using a spring model of a mass point system where circuit blocks with no size are coupled through springs, configuring at least partial circuit blocks as circles to re-lay out the circuit blocks such that there is eliminated any overlapping among the circuit blocks, compacting the external shape of an assembly of the circuit blocks by matching the external shape with the frame of a die and altering the shape of each circuit block from the circle to an actual shape.

Claims

1. A method of generating, in an automatic electronic design apparatus, electronic final layout data corresponding to a circuit block layout for manufacturing an integrated circuit, the automatic electronic design apparatus including a layout specification memory containing electronic circuit block data corresponding to circuit blocks, a layout information memory and a processing unit, said method comprising the steps of:

(a) from the electronic circuit block data, producing electronic rough layout data corresponding to an initial layout of said circuit blocks using a spring model of a mass point system in which infinitesimal circuit blocks are coupled through springs;

(b) from the electronic rough layout data, producing electronic revised layout data corresponding to a revised layout of said circuit blocks by representing at least some of said circuit blocks as circles and eliminating overlap among the circles;

(c) from said electronic revised layout data, generating electronic compacted layout data corresponding to a compacted layout of said circuit blocks to match an external perimeter shape of said circuit blocks as a whole with a frame of a die of the integrated circuit;

(d) altering the electronic compacted layout data to form electronic reshaped layout data corresponding to a layout of reshaped circuit blocks where the representation of the at least some of said circuit blocks is reshaped from a circle to an actual shape;

(e) from the electronic reshaped layout data, generating electronic expanded layout data corresponding to an expanded layout of circuit blocks by expanding each circuit block to provide a region for wiring;

(f) from the electronic expanded layout data, producing electronic fixed layout data by fixing positions of said circuit blocks after adjusting an aspect ratio of each circuit block within a corresponding allowable range; and

(g) from electronic fixed layout data, producing the electronic final layout data by wiring within and between fixed circuit blocks.

2. The method of claim 1 wherein said circuit blocks are represented as circles and rectangles.

3. The method of claim 1 wherein said electronic rough layout data corresponding to the initial layout is established based on an assumption of a free boundary using a spring model of an attractive force balancing type where only the attractive force is exerted between two circuit blocks based on an intercentral distance between the two circuit blocks.

4. The method of claim 1 wherein said step of producing electronic revised layout data is performed based on a free boundary condition using a spring model of an attractive/repulsive balancing type where an attractive and a repulsive force is exerted between two circuit blocks based on an intercentral distance between the two circuit blocks.

5. The method of claim 1 wherein:

said step of generating electronic compacted layout data uses a spring model of an attractive force balancing type where only the attractive force is exerted between two circuit blocks based on an intercentral distance between the circuit blocks when the two circuit blocks are non-overlapping;

said step of generating electronic compacted layout data uses a spring model of a repulsive force balancing type where only the repulsive force is exerted between the two circuit blocks based on the intercentral distance between the two circuit blocks when the two circuit blocks are partly overlapped; and

a die frame is assumed as a boundary condition.

6. The method of claim 1 wherein at least one step among said steps of generating electronic compacted layout data, altering the electronic compacted layout data, generating electronic expanded layout data, and producing the electronic final layout data uses a spring model of a repulsive force balancing type where only the repulsive force is exerted between two circuit blocks based on an intercentral distance between the two circuit blocks, and a die frame is assumed as a boundary condition.

7. The method of claim 1 wherein said step of producing the electronic final layout data fixes the aspect ratio except for a wiring region for each individual circuit block for which alteration of the shape of the individual circuit block is impossible.

8. The method of claim 1 wherein said spring model is expressed by a balancing equation as follows:

space="preserve" listing-type="equation">f=-c.sub.ij (L-a.sub.ij),

where f is an attractive force exerted between a circuit block i and a circuit block j,

c_ij is a number of wire connections between the circuit block i and the circuit block j,

a_ij is an intercentral distance between the circuit block i and the circuit block j when both circuit blocks make contact with each other, and

L is a general intercentral distance between the circuit block i and the circuit block j.

9. The method of claim 1 wherein said spring model is expressed by a balancing equation as follows:

space="preserve" listing-type="equation">f=-k.sub.ij ·

a.sub.ij.sup.2 /L.sup.2,

where f is a repulsive force exerted between a circuit block i and a circuit block j,

k_ij is an empirical constant relating the circuit block i to the circuit block j,

a_ij is an intercentral distance between the circuit block i and the circuit block j when both circuit blocks make contact with each other, and

L is a general intercentral distance between the circuit block i and the circuit block j.

10. The method of claim 1 wherein said spring model is expressed by a balancing equation as follows:

space="preserve" listing-type="equation">f=c.sub.ij (L-a.sub.ij)+k.sub.ij ·

a.sub.ij.sup.2 /L.sup.2,

where f is one of an attractive and a repulsive force exerted between a circuit block i and a circuit block j,

c_ij is a number of wire connections between the circuit block i and the circuit block j,

a_ij is an intercentral distance between the circuit block i and the circuit block j when both circuit blocks make contact with each other,

L is a general intercentral distance between the circuit block i and the circuit block j, and

k_ij is an empirical constant relating the circuit block i to the circuit block j.

11. An automatic electronic design apparatus having a layout specification memory containing electronic circuit block data corresponding to circuit blocks for generating electronic final layout data corresponding to a circuit block layout for manufacturing an integrated circuit comprising:

(a) means for producing, from the electronic circuit block data, electronic rough layout data corresponding to an initial layout of said circuit blocks using a spring model of a mass point system having an attractive force corresponding to a number of wire connections between said circuit blocks;

(b) means for producing, from the electronic rough layout data, electronic revised layout data corresponding to a revised layout of said circuit blocks using a spring model having a repulsive force corresponding to a degree of overlapping between said circuit blocks such that any overlapping among said circuit blocks according to said initial layout is eliminated; and

(c) means for fixing, from the electronic revised layout data, electronic fixed layout data by fixing positions of said circuit blocks after adjusting a layout of said circuit blocks corresponding to a compacted layout of said circuit blocks such that said circuit blocks are laid out regularly in a matrix form; and

(d) means for generating, from the electronic fixed layout data, the electronic final layout data by wiring between fixed circuit blocks.

12. The automatic electronic design apparatus of claim 11 further comprising means for entering the electronic circuit block data based on a function of a corresponding circuit block and for storing the electronic circuit block data in the layout specification memory.

13. The automatic electronic design apparatus of claim 12 wherein said apparatus further includes:

macro circuit block forming means for producing, from the electronic circuit block data, electronic macro circuit block data corresponding to an assembly of a plurality of said circuit blocks; and

integration/layout processing means for integrating said electronic macro circuit block data with said electronic circuit block data so that said electronic final layout data is generated using said electronic macro circuit block data as electronic circuit block data.

14. The automatic electronic design apparatus of claim 12 wherein said apparatus further includes:

means for generating electronic circumscribed frame data corresponding to a rectangular circumscribed frame around said circuit blocks arranged according to said electronic revised layout data;

means for altering said electronic circumscribed frame data by compression;

means for calculating electronic area data corresponding to an area of a dead space where no circuit block exists; and

means for further altering said electronic circumscribed frame data by compression when said calculated electronic area data indicates that the dead space exceeds a predetermined area value and for compacting the electronic compacted layout data until said calculated electronic area data indicates that the dead space is less than said predetermined area value.

15. The automatic electronic design apparatus of claim 14 wherein said apparatus further includes:

means for altering said electronic circumscribed frame data by expansion;

means for calculating electronic overlap data corresponding to a degree of overlap between said circuit blocks; and

means for further altering the electronic circumscribed frame data by expansion when the calculated electronic overlap data indicates that the degree of overlap exceeds a predetermined overlap value, and expanding the electronic compacted layout data until said electronic overlap data indicates that the degree of overlap is less than the predetermined overlap value while continuing a balancing use of the repulsive force of the spring model.

16. The automatic electronic design apparatus of claim 12 wherein said means for generating electronic compacted layout data includes:

means for calculating electronic distance data corresponding to intercentral coordinate distances between each one of said circuit blocks arranged according to said electronic revised layout data and all circuit blocks laid out regularly; and

means for selecting electronic select distance data from the electronic distance data corresponding to a select circuit block which has a minimum intercentral distance and for altering the electronic compacted layout data based on a moving of the select circuit block to a corresponding regular position.

17. The automatic electronic design apparatus of claim 12 further comprising means for producing electronic function data corresponding to a function of fixed circuit blocks.