Single element security fusible link

• US 5,309,394 A
• Filed: 09/08/1993
• Issued: 05/03/1994
• Est. Priority Date: 09/13/1990
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: NCR Corporation
• Inventors: Wuertz, William J., Stefek, Steven K., McKinley, William W.
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US08/118,161
• Time in Patent Office: 237 Days
• Field of Search: 365/52, 365/63, 365/189.03, 365/225.7, 365/200, 365/201, 307/202.1, 307/296.5, 307/303.1, 307/465, 307/565
• US Class Current: 365/189.03
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

An I/O circuit including first and second I/O pads, a fuse connected between the first pad and a RAM write enable line, and a diode-connected transistor connected between the RAM write enable line and second pad. Data is written to the RAM by applying a voltage potential to the pads after which the fuse is blown by increasing the potential difference. Other forms of the invention include a resistor connected between the RAM write enable line and ground, and I/O lines connected between the pads, respectively, and a logic circuit.

Claims

1. A method of using an I/O pad of an integrated circuit chip, with the I/O pad being connected to a logic circuit, and further with the integrated circuit chip having a memory connected to a write enable line, comprising the steps of:

connecting a fuse between the I/O pad and the write enable line;

applying a first voltage potential to the I/O pad so as to access the write enable line and allow data to be written to the memory;

applying a second voltage potential to the I/O pad so as to blow the fuse and prevent access to the write enable line; and

accessing the logic circuit through the I/O pad.

2. The method of claim 1, wherein the second voltage potential applying step is performed after the first voltage potential applying step.

3. The method of claim 2, wherein the accessing step is performed after the second voltage potential applying step.

4. The method of claim 1, wherein the second voltage potential is greater than the first voltage potential.

5. A method of using an I/O pad of an integrated circuit chip having a memory and a logic circuit, comprising the steps of:

connecting a fuse between the I/O pad and a write enable line of the memory;

accessing the write enable line through the I/O pad so as to allow data to be stored in the memory;

applying a voltage potential to the I/O pad so as to blow the fuse and prevent further access to the write enable line; and

accessing an I/O line of the logic circuit through the I/O pad so as to access the logic circuit.

6. The method of claim 5, wherein the voltage potential applying step is performed after the write enable line accessing step.

7. The method of claim 6, wherein the I/O line accessing step is performed after the voltage potential applying step.

8. A method of using an I/O pad of an integrated circuit chip, with the I/O pad being connected to a logic circuit, and with the integrated circuit chip having a memory connected to a write enable line, and further with a fuse being connected between the I/O pad and the write enable line, comprising the steps of:

applying a first voltage potential to the I/O pad so as to access the write enable line and allow data to be written to the memory;

applying a second voltage potential to the I/O pad so as to blow the fuse and prevent access to the write enable line; and

accessing the logic circuit through the I/O pad.

9. The method of claim 8, wherein the second voltage potential applying step is performed after the first voltage potential applying step.

10. The method of claim 9, wherein the accessing step is performed after the second voltage potential applying step.

11. The method of claim 8, wherein the second voltage potential is greater than the first voltage potential.