Programmable multi-format display controller

• US 5,309,552 A
• Filed: 10/18/1991
• Issued: 05/03/1994
• Est. Priority Date: 09/20/1988
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Temnycky, Walter G., Mitchell, Ralph C., Horton, Robert S.
• Primary Examiner(s): Nguyen, Phu K.
• Application Number:
  US07/782,889
• Time in Patent Office: 928 Days
• Field of Search: 364/518, 364/521, 364/522, 340/747, 340/750, 340/798, 340/799, 382/48, 395/150, 395/151, 395/129, 395/131
• US Class Current: 345/639
• CPC Class Codes: G09G 1/285 Interfacing with colour displays, e.g. TV receiver
• CPC Class Codes: G09G 5/391 Resolution modifying circuits, e.g. variable screen formats

Abstract

A programmable display controller allows reconfiguration of bit plane memory and video output connections based upon the type of display device employed. The display controller allows for the definition of multiple bit planes when the display device supports color or multiple gray shades. Simultaneous storage of images to all defined planes is accomplished through the use of multi-store logic. Multi-store logic transforms a data stream defining foreground and background portions of an image within a given display area into a form that can be simultaneously written to the bit planes as required to create the necessary output. Under processor control, a video palette may be loaded to ensure that display output signals are routed to the correct connector pins. The routing of particular signals to particular pins is reconfigured through the selection and loading of the applicable video palette. Video connector leads are connected to the palette generated data signals or to electrical ground by means of reconfigurable jumpers. The number of bit planes and display pages can be readily modified with a multi-mode controller translating the selected mode into the required bit plane memory control signals.

Claims

1. Apparatus for generating a pixel image for display by a raster scan device, said image comprising foreground pixels and background pixels, each of said foreground and background pixels containing a plurality of bit positions and having a value at each of said bit positions, each of said bit positions having a foreground value and a background value associated therewith such that the foreground pixels have said foreground value at said bit position and the background pixels have said background value at said bit position, said apparatus comprising:

an addressable memory for storing said pixel image, said memory having locations corresponding to said pixels;

means for generating a pixel signal indicating whether a pixel is a foreground pixel or a background pixel;

storage means for storing for each of said bit positions data representing the foreground and background values associated with said bit position for said image; and

means responsive to said pixel signal and to said storage means for simultaneously generating the foreground or background values of said pixel, as determined by said pixel signal, for each of said bit positions and for storing said values in said memory at the location corresponding to said pixel.

2. Apparatus as in claim 1 in which said storage means generates one of four outputs for each of said bit positions, said means responsive to said pixel signal and to said storage means being responsive to a first output from said storage means to generate a first logic level irrespective of said pixel signal, being responsive to a second output from said storage means to generate a second logic level irrespective of said pixel signal, being responsive to a third output from said storage means to generate the logic level of said pixel signal, and being responsive to a fourth output from said storage means to generate the complement of the logic level of said pixel signal.

3. Apparatus as in claim 1 in which said memory has memory planes corresponding to said bit positions, each memory plane having locations corresponding to said pixels, said means for simultaneously generating the values of said pixel for each of said bit positions storing said values in the corresponding memory planes at the locations corresponding to said pixel.

4. In a graphics system for generating a pixel image comprising and array of pixels for display by a raster scan device, said system having an addressable memory for storing said pixel image, said memory having locations corresponding to said pixels, apparatus comprising:

an addressable palette containing plural locations corresponding to respective addresses for storing words to be output via output lines to said device, said device being responsive to only a predetermined subset of said output lines, each of said words containing a predetermined number of bits corresponding to the number of said output lines, said bits having an active logic level and an inactive logic level, said palette being responsive to an address input to supply the word stored at the corresponding location to said output lines;

means for supplying an output from a location in said memory as an address input to said palette to cause the corresponding word to be supplied to said device; and

means for loading said palette with words determined in accordance with said predetermined subset of said output lines, said loading means being selectively operable to load said palette with words set at said inactive logic level at bit positions corresponding to output lines that are not part of said predetermined subset of said output lines.