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Local bus design

  • US 5,309,568 A
  • Filed: 03/16/1992
  • Issued: 05/03/1994
  • Est. Priority Date: 03/16/1992
  • Status: Expired due to Term
First Claim
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1. Computer apparatus for use with a local device (116) having address (CA, BE#), data (CD) and control (M/IO#, W/R#, ADS#) lines, and having a local bus clock signal line carrying a local bus clock signal (CLK), said local device (116) being able to initiate a local device memory address space read access cycle to a first desired address in a memory address space by placing said first address on said address lines and issuing a first predefined combination of signals on said control lines in coordination with said local bus clock signal (CLK), said local device (116) also being able to initiate a local device I/O address space read access cycle to a second desired address in an I/O address space distinct from said memory address space, by placing said second address on said address lines and issuing a second predefined combination of signals on said control lines in coordination with said local bus clock signal (CLK),for use further with a peripheral subsystem (12) receiving control signals and having peripheral subsystem port leads (DC(15:

  • 0)) carrying data, said control signals received by said peripheral subsystem (12) including a peripheral subsystem memory address space read request signal (ADMR#) and a peripheral subsystem I/O address space read request signal (CIOR#), each of said peripheral subsystem read request signals (ADMR#, CIOR#) being received by said peripheral subsystem (12) in conjunction with a respective address received by said peripheral subsystem (12), said peripheral subsystem (12) outputting data over said peripheral subsystem port leads (DB(15;

    0)) in response to said peripheral subsystem memory address space read request signal (ADMR#) if the address received by said peripheral subsystem (12) in conjunction with said peripheral subsystem memory address space read request signal (ADMR#) is within a first predefined set of addresses (A0000-BFFFF) in said memory address space, and said peripheral subsystem (12) also outputting data over said peripheral subsystem port leads (DB(15;

    0)) in response to said peripheral subsystem I/O address space read request signal (CIOR#) if the address received by said peripheral subsystem (12) in conjunction with said peripheral subsystem I/O address space read request signal (CIOR#) is within a second predefined set of addresses (3BO-3DE) in said I/O address space,for use further with an I/O bus carrying data and control signals, said I/O bus carrying an I/O bus clock signal (BCLK) having a maximum frequency which is slower than that of said local bus clock signal (CLK), said I/O bus control signals including an I/O bus memory address space read request signal (MEMR#) which when asserted indicates a read access to an address in said memory address space, said I/O bus control signals further including an I/O bus I/O address space read request signal (IOR#) which when asserted indicates a read access to an address in said I/O address space,said apparatus comprising;

    a first data path (114;

         110) which only when enabled couples any of said data on said I/O bus to said data lines of said local device (116);

    a second data path (144, 146, 148, 150;

         110) which only when enabled couples said peripheral subsystem port leads (DB(15;

    0)) to said data lines of said local device (116);

    bus interface control circuitry (114) which asserts said I/O bus memory address space read request signal (MEM#) synchronously with said I/O bus clock signal (BCLK) and enables said first data path (114;

         110), both in response to a local device memory address space read access cycle initiated by said local device (116) to an address which is outside said first predefined set of addresses (A0000-BFFFF), said first data path (114;

         110) not being enabled in response to a local device memory address space read access cycle initiated by said local device (116) to an address which is within said first predefined set of addresses (A0000-BFFFF),said bus interface control circuitry (114) further asserting said I/O bus I/O address space read request signal (IOR#) synchronously with said I/O bus clock signal (BCLK) and enabling said first data path (114;

         110), both in response to a local device I/O address space read access cycle initiated by said local device (116) to an address which is outside said second predefined set of addresses (3B0-3DE), said first data path (114;

         110) not being enabled in response to a local device I/O address space read access cycle initiated by said local device (116) to an address which is within said second predefined set of addresses (3B0-3DE); and

    peripheral subsystem control circuitry (170) which asserts said peripheral subsystem memory address space read request signal (ADMR#) synchronously with said local bus clock signal (CLK) and nonsynchronously with said I/O bus clock signal (BCLK) and which enables said second data path (144, 146, 148, 150;

         110), both in response to a local device memory address space read access cycle initiated by said local device (116) to an address which is within said first predefined set of addresses (A0000-BFFFF), said second data path (144, 146, 148, 150;

         110) not being enabled in response to a local device memory address space read access cycle initiated by said local device (116) to an address which is outside said first predefined set of addresses (A0000-BFFFF),said peripheral subsystem control circuitry (170) further enabling said second data path (144, 146, 148, 150;

         110) in response to a local device I/O address space read access cycle initiated by said local device (116) to an address which is within said second predefined set of addresses (3BO-3DE), said second data path (144, 146, 148, 150;

         110) not being enabled in response to a local device I/O address space read access cycle initiated by said local device (116) to an address which is outside said second predefined set of addresses (3BO-3DE).

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