Local bus design

• US 5,309,568 A
• Filed: 03/16/1992
• Issued: 05/03/1994
• Est. Priority Date: 03/16/1992
• Status: Expired due to Term

• Current Assignee: OPTi Incorporated
• Original Assignee: OPTi Incorporated
• Inventors: Ghosh, Subir, Lin, Fong-Lu
• Primary Examiner(s): MacDonald, Allen R.
• Assistant Examiner(s): Sheikh, Ayaz R.
• Application Number:
  US07/851,444
• Time in Patent Office: 778 Days
• Field of Search: 395/325, 395/250, 395/275, 395/425, 395/725
• US Class Current: 710/3
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

In an IBM PC AT-compatible computer architecture, CPU-generated addresses and data for accesses to a peripheral device in the I/O address space are coupled directly to the peripheral device from the local bus, without traversing the I/O bus. Any data returned from the peripheral device is coupled directly to the local bus, also without traversing the I/O bus. No buffers are needed for communicating such address and data information between the peripheral device and the I/O bus.

Claims

1. Computer apparatus for use with a local device (116) having address (CA, BE#), data (CD) and control (M/IO#, W/R#, ADS#) lines, and having a local bus clock signal line carrying a local bus clock signal (CLK), said local device (116) being able to initiate a local device memory address space read access cycle to a first desired address in a memory address space by placing said first address on said address lines and issuing a first predefined combination of signals on said control lines in coordination with said local bus clock signal (CLK), said local device (116) also being able to initiate a local device I/O address space read access cycle to a second desired address in an I/O address space distinct from said memory address space, by placing said second address on said address lines and issuing a second predefined combination of signals on said control lines in coordination with said local bus clock signal (CLK),

for use further with a peripheral subsystem (12) receiving control signals and having peripheral subsystem port leads (DC(15:

0)) carrying data, said control signals received by said peripheral subsystem (12) including a peripheral subsystem memory address space read request signal (ADMR#) and a peripheral subsystem I/O address space read request signal (CIOR#), each of said peripheral subsystem read request signals (ADMR#, CIOR#) being received by said peripheral subsystem (12) in conjunction with a respective address received by said peripheral subsystem (12), said peripheral subsystem (12) outputting data over said peripheral subsystem port leads (DB(15;

0)) in response to said peripheral subsystem memory address space read request signal (ADMR#) if the address received by said peripheral subsystem (12) in conjunction with said peripheral subsystem memory address space read request signal (ADMR#) is within a first predefined set of addresses (A0000-BFFFF) in said memory address space, and said peripheral subsystem (12) also outputting data over said peripheral subsystem port leads (DB(15;

0)) in response to said peripheral subsystem I/O address space read request signal (CIOR#) if the address received by said peripheral subsystem (12) in conjunction with said peripheral subsystem I/O address space read request signal (CIOR#) is within a second predefined set of addresses (3BO-3DE) in said I/O address space,

for use further with an I/O bus carrying data and control signals, said I/O bus carrying an I/O bus clock signal (BCLK) having a maximum frequency which is slower than that of said local bus clock signal (CLK), said I/O bus control signals including an I/O bus memory address space read request signal (MEMR#) which when asserted indicates a read access to an address in said memory address space, said I/O bus control signals further including an I/O bus I/O address space read request signal (IOR#) which when asserted indicates a read access to an address in said I/O address space,

said apparatus comprising;

a first data path (114;

     110) which only when enabled couples any of said data on said I/O bus to said data lines of said local device (116);

a second data path (144, 146, 148, 150;

     110) which only when enabled couples said peripheral subsystem port leads (DB(15;

0)) to said data lines of said local device (116);

bus interface control circuitry (114) which asserts said I/O bus memory address space read request signal (MEM#) synchronously with said I/O bus clock signal (BCLK) and enables said first data path (114;

     110), both in response to a local device memory address space read access cycle initiated by said local device (116) to an address which is outside said first predefined set of addresses (A0000-BFFFF), said first data path (114;

     110) not being enabled in response to a local device memory address space read access cycle initiated by said local device (116) to an address which is within said first predefined set of addresses (A0000-BFFFF),

said bus interface control circuitry (114) further asserting said I/O bus I/O address space read request signal (IOR#) synchronously with said I/O bus clock signal (BCLK) and enabling said first data path (114;

     110), both in response to a local device I/O address space read access cycle initiated by said local device (116) to an address which is outside said second predefined set of addresses (3B0-3DE), said first data path (114;

     110) not being enabled in response to a local device I/O address space read access cycle initiated by said local device (116) to an address which is within said second predefined set of addresses (3B0-3DE); and

peripheral subsystem control circuitry (170) which asserts said peripheral subsystem memory address space read request signal (ADMR#) synchronously with said local bus clock signal (CLK) and nonsynchronously with said I/O bus clock signal (BCLK) and which enables said second data path (144, 146, 148, 150;

     110), both in response to a local device memory address space read access cycle initiated by said local device (116) to an address which is within said first predefined set of addresses (A0000-BFFFF), said second data path (144, 146, 148, 150;

     110) not being enabled in response to a local device memory address space read access cycle initiated by said local device (116) to an address which is outside said first predefined set of addresses (A0000-BFFFF),

said peripheral subsystem control circuitry (170) further enabling said second data path (144, 146, 148, 150;

     110) in response to a local device I/O address space read access cycle initiated by said local device (116) to an address which is within said second predefined set of addresses (3BO-3DE), said second data path (144, 146, 148, 150;

     110) not being enabled in response to a local device I/O address space read access cycle initiated by said local device (116) to an address which is outside said second predefined set of addresses (3BO-3DE).

2. Apparatus according to claim 1, wherein said bus interface control circuitry (114) asserts said I/O bus I/O address space read request signal (IOR#) synchronously with said I/O bus clock signal (BCLK) also in response to a local device I/O address space read access cycle initiated by said local device (116) to an address which is within said second predefined set of addresses (3BO-3DE).

3. Apparatus according to claim 1, wherein said apparatus lacks any data path coupling data on said peripheral subsystem port leads (DB(15:

0)) to said I/O bus during the occurrence of any of said local device read access cycles initiated by said local device (116).

4. Apparatus according to claim 1, wherein said I/O bus further has address lines carrying addresses, further comprising:

a first address path (110;

     114) which only when enabled coupled to any address on said address lines of said local device (116) to said address lines of said I/O bus; and

a second address path (110;

140,

     142) which only when enabled coupled any address on said address lines of said local device (116) to said peripheral subsystem (12),

wherein said bus interface control circuitry (114) also enables said first address path (110;

     114) in response to a local device memory address space read access cycle initiated by said local device (116) to an address which is outside said first predefined set of addresses (A0000-BFFFF), and also enables said first address path (110;

     114) in response to a local device I/O address space read access cycle initiated by said local device (116) to an address which is outside said second predefined set of address (3B0-3DE), and

wherein said peripheral subsystem control circuitry (170) also enables said second address path (110;

140,

     142) during the occurrence of a local device memory address space read access cycle initiated by said local device (116) to an address which is within said first predefined set of addresses (A0000-BFFFF), and also enables said second address path (110;

140,

     142) during the occurrence of a local device I/O address space read access cycle initiated by said local device (116) to an address which is within said second predefined set of addresses (3B0-3DE).

5. Apparatus according to claim 4, wherein said apparatus lacks any path coupling addresses from said address lines of said I/O bus to said peripheral subsystem (12) during the occurrence of any of said local device read access cycles initiated by said local device (116).

6. Apparatus according to claim 4, wherein said peripheral subsystem port leads (DB(15:

0)) are multiplexed to carry said addresses received by said peripheral subsystem (12) as well as carrying said data outputted by said peripheral subsystem (12), said peripheral subsystem (12) further outputting multiplexing control signals (ADRE#;

RDMH#, RDML#) and issuing a predetermined change in said multiplexing control signals (ADRE#, RDMH#, RDML#) after receiving one of said peripheral subsystem read request signals (ADMR#, CIOR#) and before outputting data in response to said one of said peripheral subsystem read request signals (ADMR#, CIOR#), said peripheral subsystem control circuitry (170) receiving said multiplexing control signals (ADRE#;

RDMH#, RDML#),

wherein said enabling of said second address path (110;

140,

     142) during the occurrence of a local device read access cycle initiated by said local device (116) begins prior to said receipt by said peripheral subsystem control circuitry (170) of said predetermined change in said multiplexing control signals (ADRE#;

RDMH ;

RDML#) and terminates in response to said receipt by said peripheral subsystem control circuitry (170) of said predetermined change in said multiplexing control signals (ADRE#;

RDMH#, RDML#),

and wherein said enabling of said second data path (144, 146, 148, 150;

     110) in response to said local device read access cycles initiated by said local device (116) occurs only after said receipt by said peripheral subsystem control circuitry (170) of said predetermined change in said multiplexing control signals (ADRE#;

RDMH#, RDML#).

7. Apparatus according to claim 4, wherein said peripheral subsystem (12) further has high order address leads (DB(23:

16)), said high order address leads (DB(23;

16)) being connected to corresponding ones of said address lines (CA) of said local device (116).

8. Computer apparatus for use with a local device (116) having address (CA, BE#), data (CD) and control (M/IO#, W/R#, ADS#) lines, and having a local bus clock signal carrying a local bus clock signal (CLK), said local device (116) being able to initiate a local device memory address space write access cycle to a first desired address in a memory address space by placing said first address on said address lines and issuing a first predefined combination of signals on said control lines in coordination with said local bus clock signal (CLK), said local device (116) also being able to initiate a local device I/O address space write access cycle to a second desired address in an I/O address space distinct from said memory address space, by placing said second address on said address lines and issuing a second predefined combination of signals on said control lines in coordination with said local bus clock signal (CLK),

for use further with a peripheral subsystem (12) receiving control signals and having peripheral subsystem port leads (DB(15:

0)) carrying data, said control signals received by said peripheral subsystem (12) including a peripheral subsystem memory address space write request signal (CDMW#) and a peripheral subsystem I/O address space write request signal (MIOW#), each of said peripheral subsystem write request signals (CDMW#, MIOW#) being received by said peripheral subsystem (12) in conjunction with a respective address received by said peripheral subsystem (12), said peripheral subsystem (12) writing data from said peripheral subsystem port leads (DB(15;

0)) in response to said peripheral subsystem memory address space write request signal (CDMW#) if the address received by said peripheral subsystem (12) in conjunction with said peripheral subsystem memory address space write request signal (CDMW#) is within a first predefined set of addresses (A0000-BFFFF) in said memory address space, and said peripheral subsystem (12) also writing data from said peripheral subsystem port leads (DB(15;

0)) in response to said peripheral subsystem I/O address space write request signal (MIOW#) if the address received by said peripheral subsystem (12) in conjunction with said peripheral subsystem I/O address space write request signal (MIOW#) is within a second predefined set of addresses (3B0-3DE) in said I/O address space,

for use further with an I/O bus carrying data and control signals, said I/O bus carrying an I/O bus clock signal (BCLK) having a maximum frequency which is slower than that of said local bus clock signal (CLK), said I/O bus control signals including an I/O bus memory address space write request signal (MEMW#) which when asserted indicates a write access to an address in said memory address space, said I/O bus control signals further including an I/O bus I/O address space write request signal (IOW#) which when asserted indicates a write access to an address in said I/O address space,

said apparatus comprising;

a first data path (110;

     114) which only when enabled couples any of said data on said data lines of said local device (116) to said I/O bus;

a second data path (110;

144, 146, 148,

     150) which only when enabled couples said data lines of said local device (116) to said peripheral subsystem port leads (DB(15;

0));

bus interface control circuitry (114) which asserts said I/O bus memory address space write request signal (MEMW#) synchronously with said I/O bus clock signal (BCLK) and enables said first data path (110;

     114), both in response to a local device memory address space write access cycle initiated by said local device (116) to an address which is outside said first predefined set of addresses (A0000-BFFFF),

said bus interface control circuitry (114) further asserting said I/O bus I/O address space write request signal (IOW#) synchronously with said I/O bus clock signal (BCLK) and enabling said first data path (110;

     114), both in response to a local device I/O address space write access cycle initiated by said local device (116) to an address which is outside said second predefined set of addresses (3BO-3DE); and

peripheral subsystem control circuitry (170) which asserts said peripheral subsystem memory address space write request signal (CDMW#) synchronously with said local bus clock signal (CLK) and nonsynchronously with said I/O bus clock signal (BCLK) and which enables said second data path (110;

144, 146, 148,

     150), both in response to a local device memory address space write access cycle initiated by said local device (116) to an address which is within said first predefined set of addresses (AOOOO-BFFFF),

said peripheral subsystem control circuitry (170) further enabling said second data path (110;

144, 146, 148,

     150) in response to a local device I/O address space write access cycle initiated by said local device (116) to an address which is within said second predefined set of addresses (3BO-3DE).

9. Apparatus according to claim 8, wherein said bus interface control circuitry (114) both asserts said I/O bus I/O address space write request signal (IOW#) synchronously with said I/O bus clock signal (BCLK) and enables said first data path (110;

114), also in response to a local device I/O address space write access cycle initiated by said local device (116) to an address which is within said second predefined set of addresses (3B0-3DE).

10. Apparatus according to claim 8, wherein said apparatus lacks any data path coupling data on said I/O bus to said peripheral subsystem port leads (DB(15:

0)) during the occurrence of any of said local device write access cycles initiated by said local device (116).

11. Apparatus according to claim 8, wherein said I/O bus further has address lines carrying addresses, further comprising:

a first address path (110;

     114) which only when enabled couples any address on said address lines of said local device (116) to said address lines of said I/O bus; and

a second address path (110;

140,

     142) which only when enabled couples any address on said address lines of said local device (116) to said peripheral subsystem (12),

wherein said bus interface control circuitry (114) also enables said first address path (110;

     114) in response to a local device memory address space write access cycle initiated by said local device (116) to an address which is outside said first predefined set of addresses (A0000-BFFFF), and also enables said first address path (110;

     114) in response to a local device I/O address space write access cycle initiated by said local device (116) to an address which is outside said second predefined set of addresses (3BO-3DE), and

wherein said peripheral subsystem control circuitry (170) also enables said second address path (110;

140,

     142) during the occurrence off a local device memory address space write access cycle initiated by said local device (116) to an address which is within said first predefined set of addresses (A0000-BFFFF), and also enables said second address path (110;

140,

     142) during the occurrence of a local device I/O address space write access cycle initiated by said local device (116) to an address which is within said second predefined set of addresses (3BO-3DE).

12. Apparatus according to claim 11, wherein said apparatus lacks any path coupling addresses from said address lines of said I/O bus to said peripheral subsystem (12) during the occurrence of any of said local device write access cycles initiated by said local device (116).

13. Apparatus according to claim 11, wherein said peripheral subsystem port leads (DB(15:

0)) are multiplexed to carry said addresses received by said peripheral subsystem (12) as well as carrying said data to be written by said peripheral subsystem (12), said peripheral subsystem (12) further outputting multiplexing control signals (ADRE#;

RDMH#, RDML#) and issuing a predetermined change in said multiplexing control signals (ADRE#;

RDMH#, RDML#) after receiving one of said peripheral subsystem write request signals (CDMW#, MIOW#) and before writing data in response to said one of said peripheral subsystem write request signals (CDMW#, MIOW#), said peripheral subsystem control circuitry (170) receiving said multiplexing control signals (ADRE#;

RDMH#, RDML#),

wherein said enabling of said second address path (110;

140,

     142) during the occurrence of a local device write access cycle initiated by said local device (116) begins prior to said receipt by said peripheral subsystem control circuitry (170) of said predetermined change in said multiplexing control signals (ADRE#, RDMH#, RDML#) and terminates in response to said receipt by said peripheral subsystem control circuitry (170) of said predetermined change in said multiplexing control signals (ADRE#;

RDMH#, RDML#),

and wherein said enabling of said second data path (110;

144, 146, 148,

     150) in response to said local device write access cycles initiated by said local device (116) occurs only after said receipt by said peripheral subsystem control circuitry (170) of said predetermined change in said multiplexing control signals (ADRE#;

RDMH#, RDML#).

14. Apparatus according to claim 8, wherein said local device (116) is further able to initiate a local device memory address space read access cycle to a third desired address in said memory address space by placing said third address on said address lines and issuing a third predefined combination of signals on said control lines in coordination with said local bus clock signal (CLK), said local device (116) also being able to initiate a local device I/O address space read access cycle to a fourth desired address in said I/O address space, by placing said fourth address on said address lines and issuing a fourth predefined combination of signals on said control lines in coordination with said local bus clock signal (CLK),

wherein said control signals received by said peripheral subsystem (12) further includes a peripheral subsystem memory address space read request signal (ADMR#) and a peripheral subsystem I/O address space read request signal (CIOR#), each of said peripheral subsystem rad request signals (ADMR#, CIOR#) being received by said peripheral subsystem (12) in conjunction with a respective address received by said peripheral subsystem (12), said peripheral subsystem (12) outputting data over said peripheral subsystem port leads (DB(15:

0)) in response to said peripheral subsystem memory address space read request signal (ADMR#) if the address received by said peripheral subsystem (12) in conjunction with said peripheral subsystem memory address space read request signal (ADMR#) is within said first predefined set of addresses (A0000-BFFFF) in said memory address space, and said peripheral subsystem (12) also outputting data over said peripheral subsystem port leads (DB(15;

0)) in response to said peripheral subsystem I/O address space read request signal (CIOR#) if the address received by said peripheral subsystem (12) in conjunction with said peripheral subsystem I/O address space read request signal (CIOR#) is within said second predefined set of addresses (3B0-3DE) in said I/O address space,

wherein said I/O bus control signals further include an I/O bus memory address space read request signal (MEMR#) which when asserted indicates a read access to an address in said memory address space, said I/O bus control signals further including an I/O bus I/O address space read request signal (IOR#) which when asserted indicates a read access to an address in said I/O address space,

said apparatus further comprising;

a third data path (114;

     110) which only when enabled couples any of said data on said I/O bus to said data lines of said local device (116); and

a fourth data path (144, 146, 148, 150;

     110) which only when enabled couples said peripheral subsystem port leads (DB(15;

0)) to said data lines of said local device (116),

wherein said bus interface control circuitry (114) further asserts said I/O bus memory address space read request signal (MEMR#) synchronously with said I/O bus clock signal (BCLK) and enables said third data path (114;

     110), both in response to a local device memory address space read access cycle initiated by said local device (116) to an address which is outside said first predefined set of addresses (A0000-BFFFF), said third data path (114;

     110) not being enabled in response to a local device memory address space read access cycle initiated by said local device (116) to an address which is within said first predefined set of addresses (A0000-BFFFF),

said bus interface control circuitry (114) further asserting said I/O bus I/O address space read request signal (IOR#) synchronously with said I/O bus clock signal (BCLK) and enabling said third data path (114;

     110), both in response to a local device I/O address space read access cycle initiated by said local device (116) to an address which is outside said second predefined set of addresses (3B0-3DE), said third data path (114;

     110) not being enabled in response to a local device I/O address space read access cycle initiated by said local device (116) to an address which is within said second predefined set of addresses (3B0-3DE),

and wherein said peripheral subsystem control circuitry (170) further asserts said peripheral subsystem memory address space read request signal (ADMR#) synchronously with said local bus clock signal (CLK) and nonsynchronously with said I/O bus clock signal (BCLK) and which enables said fourth data path (144, 146, 148, 150;

     110), both in response to a local device memory address space read access cycle initiated by said local device (116) to an address which is within said first predefined set of addresses (A0000-BFFFF), said fourth data path (144, 146, 148, 150;

     110) not being enabled in response to a local device memory address space read access cycle initiated by said local device (116) to an address which is outside said first predefined set of addresses (A0000-BFFFF),

said peripheral subsystem control circuitry (170) further enabling said fourth data path (144, 146, 148, 150;

     110) in response to a local device I/O address space read access cycle initiated by said local device (116) to an address which is within said second predefined set of addresses (3BO-3DE), said fourth data path (144, 146, 148, 150;

     110) not being enabled in response to a local device I/O address space read access cycle initiated by said local device (116) to an address which is outside said second predefined set of addresses (3B0-3DE).

15. Apparatus according to claim 14, wherein said apparatus lacks any data path coupling data between said I/O bus and said peripheral subsystem port leads (DB(15:

0)) during the occurrence of any of said local device access cycles initiated by said local device (116).

16. Apparatus according to claim 14, wherein said I/O bus further has address lines carrying addresses, further comprising:

a first address path (110;

     114) which only when enabled couples any address on said address lines of said local device (116) to said address lines of said I/O bus; and

a second address path (110;

140,

     142) which only when enabled couples any address on said address lines of said local device (116) to said peripheral subsystem (12),

wherein said bus interface control circuitry (114) also enables said first address path (110;

     114) in response to a local device memory address space write access cycle initiated by said local device (116) to an address which is outside said first predefined set of addresses (A0000-BFFFF), and also enables said first address path (110;

     114) in response to a local device I/O address space write access cycle initiated by said local device (116) to an address which is outside said second predefined set of addresses (3B0-3DE), and also enables said first address path (110;

     114) in response to a local device memory address space read access cycle initiated by said local device (116) to an address which is outside said first predefined set of addresses (A0000-BFFFF), and also enables said first address path (110;

     114) in response to a local device I/O address space read access cycle initiated by said local device (116) to an address which is outside said second predefined set of addresses (3BO-3DE), and

wherein said peripheral subsystem control circuitry (170) also enables said second address path (110;

140,

     142) during the occurrence of a local device memory address space write access cycle initiated by said local device (116) to an address which is within said first predefined set of addresses (A0000-BFFFF), and also enables said second address path (110;

140,

     142) during the occurrence of a local device I/O address space write access cycle initiated by said local device (116) to an address which is within said second predefined set of addresses (3B0-3DE), and also enables said second address path (110;

140,

     142) during the occurrence of a local device memory address space read access cycle initiated by said local device (116) to an address which is within said first predefined set of addresses (A0000-BFFFF), and also enables said second address path (110;

140,

     142) during the occurrence of a local device I/O address space read access cycle initiated by said local device (116) to an address which is within said second predefined set of addresses (3B0-3DE).

17. Apparatus according to claim 16, wherein said apparatus lacks any path coupling addresses from said address lines of said I/O bus to said peripheral subsystem (12) during the occurrence of any of said local device access cycles initiated by said local device (116).

18. Apparatus according to claim 14, wherein said peripheral subsystem comprises a video controller and a video memory array, said video controller having video control registers accessible within a predefined video control register address range in said I/O address space,

wherein said first predefined set of addresses is included in the address range A0000h-BFFFFh,

and wherein said second predefined set of addresses is said predefined video control register address range.

19. Computer apparatus comprising:

a CPU subsystem (116,

     110) having address leads (CA, BE#), data leads (CD) and control leads (M/IO#, ADS#);

an I/O subsystem (112, 120, 122, 154, 124,

     126) having address leads (SA, LA, XA) and data leads (SD, XD);

a video controller (12) having address leads (A(19;

16), DB(15;

0)) and data leads (DB(15;

0));

interface coupling circuitry (in

     114) coupled to communicate data only when enabled, between said CPU subsystem data leads (CD) and at least some of said I/O subsystem data leads (SD, XD);

a data buffer (144, 146;

148,

     150) connected directly between said CPU subsystem data leads (CD) and said video controller data leads (DB(15;

0)), said data buffer communicating data between said CPU subsystem data leads (CD) and said video controller data leads (DB(15;

0)) only when enabled; and

control means for enabling said interface coupling circuitry (114) in response to a first predefined combination of signals (M/IO#=M;

ADS#=Active) on said CPU subsystem control leads only when said CPU subsystem address leads (CA, BE#) carry an address which is within a first predefined set of addresses,

and for enabling said data buffer (144, 146;

148,

     150) in response to said first predefined combination of signals (M/IO#=M;

ADS#=Active) on said CPU subsystem control leads only when said CPU subsystem address leads (CA, BE#) carry an address which is within a second predefined set of addresses distinct from said first predefined set of addresses.

said apparatus lacking any buffers connected directly between any of said I/O subsystem data leads (SD, XD) and said video controller data leads (DB(15;

0)).

20. Apparatus according to claim 19, for use where CPU subsystem (116, 110) supports first and second distinct address spaces (memory address space;

I/O address space), and wherein said control leads include an address space selection lead carrying an address space selection signal (M/IO#) indicating which of said distinct address spaces are referred to by an address on said CPU subsystem address leads (CA, BE#),

wherein said first and second predefined sets of addresses are in said first address space and wherein said address space selection signal (M/IO#) in said first predefined combination of signals indicates said first address space and not said second address space.

21. Apparatus according to claim 20, wherein said control means is further for enabling said interface coupling circuitry in response to a second predefined combination of signals (M/IO#=IO;

ADS#=Active) on said CPU subsystem control leads only when said CPU subsystem address leads (CA, BE#) carry an address which is within a third predefined set of addresses,

an is further for enabling said data buffer (144, 146;

148,

     150) in response to said second predefined combination of signals (M/IO#=IO;

ADS#=Active) on said CPU subsystem control leads only when said CPU subsystem address leads (CA, BE#) carry an address which is within a fourth predefined set of addresses distinct from said third predefined set of addresses,

wherein said third and fourth predefined sets of addresses are in said second address space and wherein said address space selection signal (M/IO#) in said predefined combination of signals indicates said second address space and not said first address space.

22. Apparatus according to claim 19, wherein at least a first subset (A(19:

16)) of said address leads of said video controller (12) are connected to receive all signals which are carried by corresponding respective ones (CA(19;

16)) of said address leads of said CPU subsystem (116,

     110).

23. Apparatus according to claim 22, wherein a second subset (DB(15:

2)) of said video controller address leads are multiplexed with said video controller data leads, said second subset being distinct from said first subset (A(19;

16)),

further comprising an address buffer (140,

     142) connected between said second subset of video controller address leads (DB(15;

2) and a corresponding subset (CA(15;

2)) of said CPU subsystem address leads, said address buffer (140,

     142) communicating address information from said subset (CA(15;

2)) of said CPU subsystem address leads to said second subset of video controller address leads (DB(15;

2)) only when enabled,

said control means being further for enabling said address buffer whenever said CPU subsystem data leads (CD) are not in communication with said second subset of video controller address leads (DB(15;

2)).