PROM and ROM memory cells

• US 5,311,039 A
• Filed: 04/22/1991
• Issued: 05/10/1994
• Est. Priority Date: 04/24/1990
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Kimura, Masakazu, Kondo, Toshihiko
• Primary Examiner(s): Crane, Sara W.
• Application Number:
  US07/689,222
• Time in Patent Office: 1,114 Days
• Field of Search: 257/50, 257/73, 257/529, 257/530, 257/391, 257/756, 257/922
• US Class Current: 257/50
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: Y10S 257/91 Diode arrays, e.g. diode read-only memory array

Abstract

An antifuse memory cell having a P⁺ polysilicon doping in a region directly under an intrinsic silicon programming layer. The P⁺ polysilicon region is surrounded by an N^- polysilicon doped region, and the two regions are sandwiched between layers of silicon dioxide insulation. The interface between the two regions is a P-N junction, in fact, a diode. The diode does not suffer from a diffusion current that increases with increasing levels of N^- doping, therefore the N^- polysilicon can be heavily doped to yield a very conductive bit line interconnect for a memory matrix. The interconnect line widths can be very narrow, and further microminiaturization is aided thereby. The top metalization is aluminum and serves as a word line interconnect in the memory matrix.

Claims

1. An antifuse PROM memory device formed on a substrate, comprising:

a first insulation layer on the substrate;

a silicon layer on the first insulation layer, the silicon layer including regions having a first conductivity type and a region having a second conductivity type opposite to the first type so that at least one P-N junction diode is formed substantially in parallel with the first insulation layer;

a second insulation layer on the silicon layer, the second insulation layer including a contact hole which exposes a portion of the region having the second conductivity type in the silicon layer;

antifuse means in the contact hole and vertically in contact with the portion of the region exposed in the silicon layer for allowing programming of the device such that the antifuse means is directly connected to the P-N junction diode in the forward direction of the P-N junction diode; and

a conductive layer on the antifuse means.

16. The device of claim 1, wherein the first conductivity type is an n-type and the second conductivity is a p-type.

17. The device of claim 16, wherein a region of the second conductivity type is sandwiched between two regions of the first conductivity type in the silicon layer.

2. A semiconductor device formed on a substrate, comprising:

a first insulation layer on the substrate;

a first silicon layer on the first insulation layer;

a second insulation layer on the first silicon layer, the second insulation layer including a plurality of openings;

a second silicon layer on the second insulation layer and in the openings and in contact with the first silicon layer, the second layer having an conductivity type same as that of the first silicon layer and an impurity concentration substantially lower than that of the first silicon layer;

a third insulation layer on the second silicon layer, the third insulation layer including a contact hole between the openings;

a metal layer in the contact hole and in contact with the second silicon layer to form a Schottky barrier diode; and

a wiring layer covering the contact hole.

3. The device of claim 2, wherein:

the wiring layer and the first and second silicon layers form a matrix such that the contact hole is located at an intersection thereof.

4. The device of claim 2, further comprising:

antifuse means between the metal layer and the wiring layer for allowing programming of the device.

18. The device of claim 4, wherein the first and second silicon layers have an n-type conductivity.

19. The device of claim 18, wherein the metal layer is a refractory metal layer.

5. A semiconductor device formed on a substrate, comprising:

a first insulation layer on the substrate;

a first silicon layer on the first insulation layer, the first silicon layer having a first conductivity type;

a second insulation layer on the first silicon layer, the second insulation layer including a plurality of openings;

a second silicon layer on the second insulation layer and in the openings in contact with the first silicon layer, the second silicon layer including regions having the first conductivity type and an impurity concentration substantially lower than that of the first silicon layer and a region having a second conductivity type opposite to the first type so that at least one P-N junction diode is formed substantially in parallel with the second insulation layer;

a third insulation layer on the second silicon layer, the third insulation layer including a contact hole which exposes a portion of the region having the second conductivity type in the second silicon layer, the contact hole positioned between the openings; and

a wiring layer covering the contact hole.

6. The device of claim 5, wherein:

the first silicon layer comprises a metal silicide.

7. The device of claim 5, wherein:

the first and second silicon layers are arranged in a matrix with the wiring layer, with the contact hole positioned at an intersection thereof.

20. The device of claim 5, further comprising antifuse means in the contact hole between the region exposed in the second silicon layer and the wiring layer for allowing programming of the device.

21. The device of claim 20, wherein the first conductivity type is an n-type and the second conductivity type is a p-type.

8. A masked read only memory (ROM) on a substrate, comprising:

a first insulation layer on the substrate;

a first conductive layer having a first conductivity type on the first insulation layer;

a second insulation layer on the first conductive layer, the second insulation layer including a plurality of apertures;

a second conductive layer including regions having the first conductivity type on the second insulation layer and regions having a second conductivity type opposite to the first type in the apertures so that at least one P-N junction diode is formed substantially in parallel with the second insulating layer;

a third insulation layer on the second conductive layer, the third insulation layer including a contact hole over an aperture, the contact hole exposing a region having the second conductivity type in the second silicon layer, the absence or presence of a contact hole over an aperture representing data; and

a third conductive layer in the contact hole and in contact with the region having the second conductivity type in the second conductive layer.

9. The ROM of claim 8, wherein:

the regions having the second conductivity type in the second conductive layer are p-type polysilicon;

the regions having the first conductivity type in the second conductive layer are n-type polysilicon;

the first and second insulation layers comprise silicon dioxide; and

the third conductive layer comprises aluminum.

10. A semiconductor device on a substrate, comprising:

a first insulation layer on the substrate;

a first conductive layer on the first insulation layer;

a second insulation layer on the first conductive layer, the second insulation layer including a plurality of apertures;

a second conductive layer on the second insulation layer and in contact with the first conductive layer in the first apertures, the second conductive layer having a conductivity type same as that of the first conductive layer;

a third insulation layer on the second conductive layer, the third insulation layer including a contact hole between the apertures, the contact hole exposing the second conductive layer;

a refractory metal silicide layer disposed within the contact hole to form a Schottky diode; and

a third conductive layer covering the contact hole and in electrical communication with the Schottky diode.

11. A semiconductor ROM memory device formed on a substrate, comprising:

a first insulation layer on the substrate;

a first conductive layer on the first insulation layer;

a second insulation layer on the first conductive layer, the second insulation layer including a plurality of apertures;

a second conductive layer on the second insulation and in contact with the first conductive layer in the apertures, the second conductive layer having a conductivity type same as that of the first conductive layer;

a third insulation layer on the second conductive layer, the third insulation layer including a contact hole positioned directly over an aperture;

a refractory metal silicide layer disposed in the contact hole and in contact with the second conductive layer to form a Schottky diode; and

a third conductive layer in contact with the metal silicide layer in the contact hole, the presence or absence of a contact hole representing data.

22. The device of claim 11, wherein the conductivity type of the first and second conductive layers are n-type.

12. A semiconductor ROM memory device formed on a substrate, comprising:

a first insulation layer on the substrate;

a first conductive layer on the first insulation layer, the first conductive layer having a first conductivity type;

a second insulation layer on the first conductive layer, the second insulation layer including a plurality of apertures;

a second conductive layer including regions having the first conductivity type in contact with the first conductive layer in the apertures and regions having a second conductivity type opposite to the first type on the second insulation layer so that at least one P-N junction is formed substantially in parallel with the second insulation layer;

a third insulation layer on the second conductive layer, the third insulation layer including a contact hole positioned directly over an aperture, the contact hole exposing a region in the second conductive layer, the presence or absence of a contact hole representing data; and

a third conductive layer covering the contact hole and in contact with the region exposed.

13. The device of claim 12, wherein:

the exposed region has the second conductivity type in the second conductive layer.

23. The device of claim 12, wherein the first conductivity type is an n-type and the second conductivity type is a p-type.

14. A semiconductor memory device formed on a substrate, comprising:

a first insulation layer on the substrate;

a first silicon layer on the first insulation layer, the first silicon layer having a first conductivity type;

a second insulation layer on the first silicon layer, the second insulation layer including a plurality of openings;

a second silicon layer on the second insulation layer and in the openings in contact with the first silicon layer, the second silicon layer including regions having the first conductivity type and an impurity concentration substantially lower than that of the first silicon layer and a region having a second conductivity type opposite to that of the first type so that at least one P-N junction diode is formed substantially in parallel with the second insulation layer;

a third insulation layer on the second silicon layer, the third insulation layer including a contact hole which exposes a portion of the region having the second conductivity type in the second silicon layer, the contact hole positioned between the openings;

a metal film in the contact hole;

a third silicon layer on the metal film; and

a wiring layer covering the contact hole.

15. The device of claim 14, wherein:

the first silicon layer is arranged in lattice form with the wiring layer, and the contact hole is located at an intersection.

24. The device of claim 14, wherein the first conductivity type is an n-type and the second conductivity type is a p-type.