Apparatus and method for full-duplex ethernet communications

• US 5,311,114 A
• Filed: 10/27/1992
• Issued: 05/10/1994
• Est. Priority Date: 10/27/1992
• Status: Expired due to Term

• Current Assignee: LSI Corporation (Broadcom, Inc.)
• Original Assignee: Seeq Technology, Inc. (Broadcom, Inc.)
• Inventors: Sambamurthy, Namakkal S., Lai, Woo-Ping, VanGilder, John P.
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US07/966,978
• Time in Patent Office: 560 Days
• Field of Search: 370/14, 370/24, 370/31, 370/85.3, 370/95.3, 455/58.2, 455/78, 455/79, 375/7, 375/121
• US Class Current: 370/296
• CPC Class Codes: H04L 12/40013 Details regarding a bus controller
• CPC Class Codes: H04L 12/40136 Nodes adapting their rate to the physical link properties LAN switches H04L49/351
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
• CPC Class Codes: H04L 12/44 Star or tree networks
• CPC Class Codes: Y10S 370/91 Carrier sense multiple access, e.g. ethernet, 10base-t

Abstract

A downward compatible full-duplex 10Base-T ethernet transceiver associated with either the hub or the remote node in an ethernet network includes generator circuitry for generating a full-duplex-capability signal indicating its full-duplex capability for transmission over the twisted pair link and detector circuitry for detecting transmission of such a signal from the transceiver with which it is communicating across the twisted pair link. The detector circuitry responds to the full-duplex-capability signal by sending a full-duplex enable signal to an ethernet controller configured according to the present invention. An ethernet controller contains circuitry responsive to the full-duplex-enable signal to disable transmission deferral in response to a carrier-sense signal generated by the transceiver. The full-duplex-capability indicator portion may comprise an extra pulse following an Nth link-integrity pulse after a delay of between about 2-7 μsec.

Claims

1. In an ethernet transceiver circuit including a transmit node and a receive node, said transmit node adapted for connection to a first transmission line to be connected to a remote receive node of a remote ethernet transceiver, and said receive node adapted for connection to a second transmission line to be connected to a remote transmit node of said remote ethernet transceiver, apparatus for implementing full duplex communication between said ethernet transceiver and said remote ethernet transceiver across said first and second pairs of conductors, comprising:

link-integrity signal generating means, coupled to said transmit node, for generating a 10Base-T link-integrity signal onto said first transmission line, said link-integrity signal including a half-duplex 10Base-T ethernet link-integrity signal, and further including a full duplex-capability-indicator portion for indicating that said ethernet transceiver is capable of full duplex communication, said full duplex-capability-indicator portion being downward compatible with half-duplex 10Base-T ethernet signal; and

full-duplex-capability detecting means, coupled to said receive node, for generating a full-duplex-mode signal in response to a full duplex-capability-indicator portion of a link-integrity signal transmitted to said receive node on said second transmission line indicating that said remote ethernet transceiver is capable of full duplex communication.

2. A 10Base-T ethernet communications controller comprising:

data transmission control circuitry for controlling data transmission to a remote ethernet transceiver

data-transmission-deferral circuitry responsive to a collision signal for deferring data transmission during time periods when data is being received;

full-duplex-mode enabling circuit means, responsive to a full-duplex mode signal, for disabling the effect of said collision signal on said data-transmission-deferral circuitry while said full-duplex-mode signal is asserted.

3. The 10Base-T ethernet communications controller of claim 2, further including means for selectively activating said full-duplex-mode enabling circuit means.

4. In an ethernet transceiver including a transmit node and a receive node, said transmit node adapted for connection to a first transmission line to be connected to a remote receive node of a remote ethernet transceiver, and said receive node adapted for connection to a second transmission line to be connected to a remote transmit node of said remote ethernet transceiver, apparatus for implementing full duplex communication across said first and second pairs of conductors, comprising:

link-integrity signal generating means, coupled to said transmit node, for generating a 10Base-T link-integrity signal onto said first transmission line, said link-integrity signal including a plurality of pulses, first and second ones of said pulses separated from one another by a period of between about 2 μ

sec and 7 μ

sec, said link-integrity signal further including N additional pulses separated from one another by between about 25 and 150 msec, where N is an integer between 1 and 20; and

full-duplex-capability detecting means, coupled to said receive node, for generating a full-duplex-mode signal in response to sensing said first and second pulses from said remote ethernet transceiver, indicating that said remote ethernet transceiver is capable of full duplex communication.

5. A 10Base-T ethernet network comprising:

an ethernet hub comprising a plurality of hub nodes, each of said hub nodes including a full-duplex-capable ethernet transceiver including a transmit node and a receive node, said transmit node adapted for connection to a first transmission line to be connected to a remote receive node of a remote ethernet transceiver, and said receive node adapted for connection to a second transmission line to be connected to a remote transmit node of said remote ethernet transceiver, each of said full-duplex-capable ethernet transceivers including link-integrity signal generating means, coupled to said transmit nodes, for generating a 10Base-T link-integrity signal onto said first transmission line, said link-integrity signal including a half-duplex 10Base-T ethernet link-integrity signal, and further including a full duplex-capability-indicator portion for indicating that said ethernet transceiver is capable of full duplex communication, said full duplex-capability-indicator portion being downward compatible with half-duplex 10Base-T ethernet signal, each of said full-duplex-capable ethernet transceivers further including full-duplex-capability detecting means, coupled to said receive nodes, for generating a full-duplex-mode signal in response to a full duplex-capability-indicator portion of a link-integrity signal transmitted to said receive nodes;

an ethernet communications controller associated with each of said full-duplex-capable ethernet transceivers, each ethernet communications controller including data-transmission-deferral circuitry coupled to a carrier-sense input for deferring data transmission in response to a signal on said carrier-sense input, each ethernet communications controller further including circuitry for enabling full-duplex operation, said circuitry comprising a full-duplex mode input and full-duplex mode enabling circuit means, coupled to said full-duplex mode input and responsive to a full-duplex mode signal asserted thereon, for disabling said data-transmission-deferral circuitry while said full-duplex mode signal is present on said full-duplex mode input.