Device for monitoring the functon of an electric load, its drive and the associated connections

• US 5,311,138 A
• Filed: 12/13/1991
• Issued: 05/10/1994
• Est. Priority Date: 04/14/1990
• Status: Expired due to Term

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Eckhardt, Jurgen, Denz, Helmut, Ott, Karl, Mayer, Rudi, Strobele, Hans-Peter, Palesch, Reinhard
• Primary Examiner(s): Wieder, Kenneth A.
• Assistant Examiner(s): TOBIN, C
• Application Number:
  US07/778,172
• Time in Patent Office: 879 Days
• Field of Search: 324/503, 324/509, 324/510, 324/522, 324/537, 340/660, 340/661, 340/650, 361/79, 361/88, 361/90
• US Class Current: 324/503
• CPC Class Codes: G01R 31/007 using microprocessors or computers
• CPC Class Codes: G01R 31/3275 Fault detection or status indication

Abstract

Circuitry for monitoring the function of electric load, an output stage and a control circuit for driving the output stage and the lines that connect these elements. The circuitry includes at least one fault acquisition logic that is connected in parallel with the output stage. The fault acquisition logic has a terminal that connects to an input of the output stage and another terminal that connects to the output of the output stage. The fault acquisition logic also is connected to a reference potential. The fault acquisition logic has a comparator for comparing potentials for determining fault conditions. Detected fault conditions may be stored in a buffer memory that connects to a main memory. The buffer memory may also have a time delay associated with it. The circuitry also may include a coder for encoding signals indicative of the fault conditions that are detected by the fault acquisition logic. The circuitry may further include a safety disconnect to protect the output stage against overload.

Claims

1. Circuitry for monitoring the function of an electric/electronic circuit, the electric/electronic circuit including an electric load, at least one output stage, a connecting line that connects the output stage to the electric load, and a control circuit that connects to the output stage, comprising:

(A) at least one fault acquisition logic circuit that is connected in parallel with the output stage, the fault acquisition logic circuit being for detecting the occurrence of fault conditions including a short circuiting of the load, a short circuiting of the output stage, and an interruption in the connecting line, the fault acquisition logic circuit further comprising,

(1) a first terminal connected to an input potential of the output stage,

(2) a second terminal connected to an output potential of the output stage,

(3) means for applying a reference potential at a predetermined level to at least one of the first and second terminals for distinguishing between a short circuiting of the output stage and an interruption in the connecting line, and

(4) comparator means for comparing at least one preselected threshold potential and potentials associated with the output stage; and

(B) storage means for storing signals indicative of detected fault conditions.

2. The circuitry as recited in claim 1, wherein the output stage includes one of inverting and non-inverting output stages.

3. The circuitry as recited in claim 1, wherein the output stage includes one of low-side and high-side output stages.

4. The circuitry as recited in claim 1, wherein the storage means includes a first memory and a second memory, with the first and second memories being connected.

5. The circuitry as recited in claim 4, wherein the first memory includes a buffer memory.

6. The circuitry as recited in claim 2, wherein the buffer memory is a temporary storage for signals indicative of detected fault conditions.

7. The circuitry as recited in claim 5, further comprising a time delay device coupled to the buffer memory.

8. The circuitry as recited in claim 1, wherein the circuitry further includes a coder means for encoding the signals indicative of detected fault conditions.

9. The circuitry as recited in claim 1, wherein the circuitry further includes a safety circuit for protecting the output stage.

10. The circuitry as recited in claim 1, wherein the storage means connects to the control circuit which inputs a control signal to the storage means for reading-out the predetermined information stored in the storage means.

11. The circuitry as recited in claim 1, wherein the circuitry includes a plurality of cascaded circuitries.