Circuit for measuring variations in the capacitance of a variable capacitor using a continuously rebalanced detection bridge

• US 5,311,140 A
• Filed: 08/28/1992
• Issued: 05/10/1994
• Est. Priority Date: 12/29/1989
• Status: Expired due to Fees

• Current Assignee: Societe D'Applications Generales D'Electricite et de Mecanique Sagem
• Original Assignee: Societe D'Applications Generales D'Electricite et de Mecanique Sagem
• Inventors: Permuy, Alfred
• Primary Examiner(s): Strecker, Gerard R.
• Assistant Examiner(s): DO, DIEP N
• Application Number:
  US07/924,049
• Time in Patent Office: 620 Days
• Field of Search: 324/132, 324/610, 324/658, 324/666, 324/673, 324/680, 364/573, 73/765, 73/766, 307/320, 307/359, 307/491, 307/494
• US Class Current: 324/680
• CPC Class Codes: G01D 5/2403 by moving plates, not forming part of the capacitor itself, e.g. shields
• CPC Class Codes: G01D 5/2417 by varying separation

Abstract

A circuit for measuring variations in the capacitance of a variable capacr forming part of a sensor includes an oscillator which generates an alternating signal which is supplied to two branches of a detection bridge. The first branch includes the variable capacitor connected in series with a variable capacitance diode. The second branch includes a capacitor connected in series with a variable capacitance diode. A differential stage has each of its in puts connected to the common point of a respective one of the branches. Synchronous demodulation means connected to the oscillator, are connected to the output of the differential stage for delivering a DC unbalance voltage Ve which is injected by a feedback line to the common point of the first branch, thereby continuously balancing the detection bridge.

Claims

1. A circuit for measuring variations in the capacitance of a variable capacitor, wherein the circuit comprises:

an oscillator generating an alternating signal;

a detection bridge comprising first and second branches connected to the oscillator, the first branch including the variable capacitor connected in series with a variable capacitance diode, while the second branch comprises a capacitor connected in series with a variable capacitance diode;

a differential stage having its inputs connected to respective ones of the branches at their common points between their capacitors and their variable capacitance diodes;

a DC bias circuit for biasing the common point of the second branch;

synchronous demodulation means following the differential stage and connected to the oscillator for delivering a DC unbalance signal; and

a feedback line injecting the unbalance signal to the common point of the first branch to continuously rebalance the detection bridge.

2. A circuit according to claim 1 wherein the synchronous demodulation means comprise a synchronous detection circuit and a lowpass filter delivering the unbalance signal.

3. A circuit according to claim 1, wherein each input of the differential stage is connected to the common point of a branch by means of a coupling capacitor.

4. A circuit according to claim 1, wherein the common points of the branches are connected respectively to the bias circuit and to the feedback line by means of bias resistors for the variable capacitance diodes.

5. A circuit according to claim 2, wherein the low-pass filter is connected to a linearization circuit for the unbalance signal, the linearization circuit comprising:

a number n of threshold differential units each receiving as inputs the unbalance signal and a respective reference voltage, and each delivering an output signal in the form of a current which varies in a manner that includes a portion of zero slope connected to a portion of determined slope by an angle point defined by the reference voltage; and

a number n of means for combining the currents from the differential units, thereby obtaining a resultant signal having multiple angle points which, when combined with the unbalance signal, enables it to be linearized.

6. A circuit according to claim 5, wherein at least one differential unit delivers an output current whose variation includes a zero slope portion for any value of the unbalance signal below the reference voltage, and a determined slope portion for any value of the unbalance signal greater than the reference voltage.

7. A circuit according to claim 5, wherein at least one of the differential units delvers an output current which varies in a manner that includes a zero slope portion for any value of the unbalance signal greater than the reference voltage, and a determined slope portion for any value of the unbalance signal less than the reference voltage.

8. A circuit according to claim 6, wherein each differential unit is constituted by a first transistor having a base connected to the reference voltage and an emitter connected via a resistor to the emitter of a second transistor whose base receives the unbalance signal, while the collector of the first transistor delivers the output current.

9. A circuit according to claim 7, wherein each differential unit is constituted by a first transistor having a base receiving the unbalance signal and an emitter which is connected via a resistor to the emitter of a second transistor whose base is connected to the reference voltage, the collector of the first transistor delivering the output current.

10. A circuit according to claim 8 or 9, wherein the emitter resistors determine the slope of the variation in the output current of the differential units.

11. A circuit according to claim 5, wherein each combination means is formed by a current mirror.

12. A circuit according to claim 11, wherein the current mirrors subtract the output currents delivered by the differential units.

13. A circuit according to claim 11, wherein the current mirrors add the output currents delivered by the differential units.

14. A circuit according to claim 1, wherein the capacitor of said second branch is variable in order to provide differential capacitance detection.