Integrated phase locked loop local oscillator

• US 5,311,149 A
• Filed: 03/12/1993
• Issued: 05/10/1994
• Est. Priority Date: 03/12/1993
• Status: Expired due to Term

• Current Assignee: Trimble Navigation Limited (Trimble Inc.)
• Original Assignee: Trimble Navigation Limited (Trimble Inc.)
• Inventors: Parker, Reed A., Wagner, Gary L., Lau, Chung Y.
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US08/030,678
• Time in Patent Office: 424 Days
• Field of Search: 331/1 A, 331/18, 331/22, 331/30, 331/31, 331/108 C, 331/117 R, 331/175, 331/183, 455/256, 455/260, 455/285, 455/293, 455/314, 455/315, 455/316
• US Class Current: 331/1.00A
• CPC Class Codes: H03D 7/163 the local oscillations of at least two of the frequency changers being derived from a single oscillator
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes

Abstract

An embodiment of the present invention is a single-chip GPS receiver front-end comprising a radio frequency amplifier, a voltage-controlled oscillator operating at a first local oscillator frequency, a divide by seven and one-half counter for deriving a second local oscillator frequency from the first and a first and second mixer. The local oscillator frequency is mid-way between two carrier frequencies of interest that may be received by the radio frequency amplifier and the first mixer produces a first intermediate frequency. The second local oscillator frequency is then beat with the first intermediate frequency in the second mixer to produce a second intermediate frequency. A dual-conversion super heterodyne configuration is therefore employed in which the first and second local oscillator frequencies are derived from a single oscillator and the first local oscillator frequency is seven and one-half times the second local oscillator frequency.

Claims

1. A dual-conversion super heterodyne receiver integrated circuit device, comprising:

a radio frequency (RF) amplifier with selection means for receiving a first frequency (F1) carrier signal and a second frequency (F2) carrier signal;

a voltage controlled oscillator (VCO) for providing a first local oscillator (LO1) signal having a frequency of approximately (F1+F2) divided by two;

a first mixer having inputs connected to respective outputs of the RF amplifier and the VCO and an output for a first intermediate frequency signal;

frequency division means connected to an output of the VCO in a phase locked loop configuration and connected to derive a second local oscillator (LO2) signal from LO1 such that LO1 divided by LO2 equals "N.5", where "N" is a positive integer; and

a second mixer having inputs derived from respective outputs of the first mixer and the frequency division means and an output for a second intermediate frequency signal.

2. The device of claim 1, wherein

said frequency F1 is approximately equal to 1575.42 MHz and said frequency F2 is approximately equal to 1227.6 MHz;

said first local oscillator LO1 signal is approximately equal to 1401.6 MHz; and

said second local oscillator LO2 signal is approximately equal to 186.88 MHz and wherein said positive integer "N" is seven.

3. The device of claim 1, wherein:

the VCO comprises an oscillator having a pair of cross-coupled amplification transistors provided for oscillator gain and a pair of feedback transistors each having its base tied to its emitter provided for capacitive positive feedback and respectively connected between the base of a first one and collector of a second one of said cross-coupled amplification transistors, wherein semiconductor process variations in the Miller capacitance of said amplification transistors are self-corrected by matching variations in the capacitance of said feedback transistors.

4. The device of claim 1, wherein:

the frequency division mans comprises a pulse-swallowing digital divider connected for a divide by seven and one-half function.

5. A dual-conversion super heterodyne receiver, comprising:

a radio frequency (RF) amplifier;

a first mixer coupled to an output of the RF amplifier for providing a first intermediate frequency output;

a phase locked loop (PLL) including a voltage controlled oscillator (VCO) with an output connected to the first mixer, a numerical counter and a phase-frequency detector for comparing an output of said numerical counter to a reference frequency for phase locked loop operation;

a divide by seven and one-half pulse-swallowing counter having an input connected to the PLL and a second local oscillator output for deriving a second local oscillator frequency one seven and a half part of said first local oscillator frequency;

a second mixer having respective inputs connected to receive said first intermediate frequency from said first mixer and a second local oscillator signal from said second local oscillator output for providing an output for a second intermediate frequency; and

an output stage with low-pass filtering and automatic gain control connected to said second intermediate frequency output of the second mixer.

6. A voltage controlled oscillator (VCO), comprising:

a pair of cross-coupled amplification transistors provided for oscillator gain and a pair of feedback transistors each having its base tied to its emitter provided for capacitive positive feedback and respectively connected between the base of a first one and collector of a second one of said cross-coupled amplification transistors, wherein semiconductor process variations in the Miller capacitance of said amplification transistors is self-corrected by matching variations in the capacitance of said feedback transistors.

7. A phase locked loop (PLL), comprising:

a voltage controlled oscillator (VCO) with an astable multivibrator including a pair of cross-coupled amplification transistors provided for oscillator gain and a pair of feedback transistors each having its base tied to its emitter provided for capacitive positive feedback and respectively connected between the base of a first one and collector of a second one of said cross-coupled amplification transistors, wherein semiconductor process variations in the Miller capacitance of said amplification transistors is self-corrected by matching variations in the capacitance of said feedback transistors;

a numeric counter means connected to divide down a sample of an output frequency produced by the VCO; and

a phase-frequency detector connected to compare an output of the numeric counter to an externally provided reference frequency and connected to lock an operating frequency of the VCO to said reference frequency.

8. The PLL of claim 7, wherein:

the numeric counter means comprises a pulse-swallowing digital divider that is connected to divide an input signal by seven and one-half.

9. The PLL of claim 8, wherein:

said pulse-swallowing digital divider includes a first D-type flip-flop and a second D-type flip-flop with an XOR-gate connected between an D-input of said second D-type flip-flop and a Q-output of said first D-type flip-flop for controlling the number of input clock transitions required to cycle both said first and second D-type flip-flops.