Method and apparatus for generating Walsh codes

• US 5,311,176 A
• Filed: 03/31/1992
• Issued: 05/10/1994
• Est. Priority Date: 03/31/1992
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Gurney, David P.
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US07/860,871
• Time in Patent Office: 770 Days
• Field of Search: 370/22, 364/727, 341/50
• US Class Current: 341/50
• CPC Class Codes: G06F 1/0255 Walsh or analogous functions
• CPC Class Codes: H04J 13/0048 Walsh
• CPC Class Codes: H04J 13/12 Generation of orthogonal codes

Abstract

A method and apparatus is provided for generating Walsh codes. A first group of address signals is generated. Subsequently, inversion control signals are generated by logically gating the first group of address signals with a second group of address signals. Finally, a Walsh code is produced by inverting elements of a predetermined vector in accordance with the generated inversion control signals.

Claims

1. A Walsh code generator, comprising:

(a) counter means for generating a first group of address signals;

(b) address means, operatively coupled to the counter means, for generating inversion control signals by logically gating the first group of address signals with a second group of address signals; and

(c) code inversion means, operatively coupled to the address means, for producing a Walsh code by inverting elements of a predetermined non-null vector through an Exclusive-OR logical gating with the generated inversion control signals.

2. The Walsh code generator of claim 1 wherein the counter means comprises a state machine selected from a group consisting essentially of a synchronous counter and an asynchronous counter.

3. The Walsh code generator of claim 1 wherein the counter means comprises a six bit length binary counter.

4. The Walsh code generator of claim 1 wherein the counter means comprises a clocking means for controlling a rate at which the Walsh codes are to be generated.

5. The Walsh code generator of claim 1 wherein the first group of address signals determines which elements of the Walsh code are to be generated.

6. The Walsh code generator of claim 1 wherein the second group of address signals determines which Walsh code is to be generated.

7. The Walsh code generator of claim 1 wherein the address means generates one of the inversion control signals by performing a logical AND of an address signal from the first group of address signals and an address signal from the second group of address signals.

8. The Walsh code generator of claim 1 wherein the code inversion means comprises a parity checker having a group of inputs and at least one output, each input receiving one of the inversion control signals from the address means, the output providing a sequence of bits representing the produced Walsh code.

9. A method of generating Walsh codes, comprising:

(a) generating a first group of address signals;

(b) generating inversion control signals by logically gating the first group of address signals with a second group of address signals; and

(c) producing a Walsh code by inverting elements of a predetermined non-null vector through an Exclusive-OR logical gating with the generated inversion control signals.

10. The method of claim 9 wherein the step of generating a first group of address signals comprises utilizing a state machine selected from a group consisting essentially of a synchronous counter and an asynchronous counter.

11. The method of claim 9 wherein the step of generating a first group of address signals comprises utilizing a six bit length binary counter.

12. The method of claim 9 wherein the step of generating a first group of address signals comprises utilizing a clocking means for controlling a rate at which the Walsh codes are to be generated.

13. The method of claim 11 wherein the first group of address signals determines which elements of the Walsh code are to be generated.

14. The method of claim 11 wherein the second group of address signals determines which Walsh code is to be generated.

15. The method of claim 11 wherein the step of generating inversion control signals comprises performing a logical AND of an address signal from the first group address signals and an address signal from the second group of address signals.

16. The method of claim 9 wherein the step of producing a Walsh code comprises utilizing a parity checker having a group of inputs and at least one output, each input receiving one of the inversion control signals, the output providing a sequence of bits representing the produced Walsh code.