Selective bulk write operation

• US 5,311,467 A
• Filed: 04/07/1992
• Issued: 05/10/1994
• Est. Priority Date: 04/07/1992
• Status: Expired due to Term

• Current Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Original Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Inventors: McClure, David C., Brady, James, Lysinger, Mark A., Slemmer, William C.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Nguyen, Tan
• Application Number:
  US07/864,481
• Time in Patent Office: 763 Days
• Field of Search: 365/189.01, 365/189.11, 365/218, 365/230.03, 365/230.05, 365/230.06
• US Class Current: 365/189.16
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A memory is disclosed having a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein. Each pair of bit lines is associated with one of the columns. A column decoder selects a column in the array responsive to a column address. A plurality of word line drivers selects, in response to a row address, a row of memory cells for connection with their associated pair of bit lines. A plurality of row isolation circuits isolates and enables a selected group of memory cells of each row from the remainder of the row in response to a bulk write signal. Each row isolation circuit has a conduction path between its associated word line driver and the selected memory cells in the associated row. A bulk write signal is sent to each column containing the selected memory cells. A first logic state is then written into the selected memory cells in response to the bulk write signal.

Claims

1. A memory in an integrated circuit, comprising:

a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein;

a plurality of pairs of bit lines, each associated with one of the columns;

a column decoder for selecting a plurality of columns in the array responsive to a column address;

a plurality of word line drivers for selecting, in response to a row address, a row of memory cells wherein each memory cell is connected to its associated pair of bit lines;

a plurality of row isolation circuits for isolating a selected group of memory cells in each row from the remainder of the row in response to a bulk write signal, each row isolation circuit having a conduction path between the selected memory cells in the associated row and the remainder of the row, wherein each row isolation circuit includes a pass gate having a conductive path and a control terminal for isolating the selected memory cells in each row from the remainder of the row in response to the bulk write signal, and an enable transistor for selecting, in response to a control signal, the selected group of memory cells; and

means for receiving the bulk write signal in each column of the selected memory cells and writing a first logic state into the selected memory cells in response to the bulk write signal.

2. The memory of claim 1, wherein each row isolation circuit further comprises:

a pair of pass transistors, each having a conductive path and a control terminal, wherein each of the pass transistors has a conductive path between the selected group of memory cells in the row and the remainder of the memory cells in the row, and wherein a first one of the pass transistors has its control terminal connected to the bulk write signal and a second one of the pass transistors has its control terminal connected to the inverse of the bulk write signal.

3. The memory of claim 2, wherein the enable transistor has a conductive path between a selected supply voltage and an output of the pass gate.

4. The memory of claim 2, wherein the pair of pass transistors comprise an n-channel transistor and a p-channel transistor.

5. The memory of claim 2, wherein the enable transistor comprises a p-channel transistor.

6. The memory of claim 1, wherein the control signal comprises the bulk write signal.

7. The memory of claim 1, wherein the control signal comprises an enable signal separate from the bulk write signal.

8. A memory in an integrated circuit, comprising:

a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein;

a plurality of pairs of bit lines, each associated with one of the columns;

a column decoder for selecting a plurality of columns in the array responsive to a column address;

a plurality of word line drivers for selecting, in response to a row address, a row of memory cells wherein each memory cell is connected to its associated pair of bit lines;

a plurality of row isolation circuits for isolating a selected group of memory cells of each row from the remainder of the row in response to a bulk write signal, each row isolation circuit having a conduction path between the selected memory cells in the associated row and the remainder of the row; and

means for receiving the bulk write signal in each column of the selected memory cells and writing a first logic state into the selected memory cells in response to the bulk write signal, each including a first pull-up transistor connected to a first bit line of its associated bit line pair and a second pull-up transistor connected to a second bit line of its associated bit line pair, and means, connected to a bit line of the bit line pair, for driving the bit line to a selected value in response to the bulk write signal.

9. The memory of claim 8, wherein the means is a first transistor.

10. The memory of claim 9, wherein the first transistor is a pull-down transistor and wherein, in response to the bulk write signal, the first pull-up transistor is turned off, the first pull-down transistor is turned on, and the bit line is pulled low.

11. A memory in an integrated circuit, comprising:

a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein;

a plurality of pairs of bit lines, each associated with one of the columns;

a column decoder for selecting a plurality of columns in the array responsive to a column address;

means for isolating a selected group of memory cells in each row from the remainder of the row in response to a bulk write signal, including a pass gate having a conductive path and a control terminal for isolating the selected memory cells in each row from the remainder of the row in response to the bulk write signal, and an enable transistor for selecting, in response to the bulk write signal, the selected group of memory cells; and

means for receiving the bulk write signal in each column of the selected memory cells and writing a first logic state into the selected memory cells in response to the bulk write signal.

12. A memory in an integrated circuit, comprising:

a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein;

a plurality of pairs of bit lines, each associated with one of the columns;

a column decoder for selecting a plurality of columns in the array responsive to a column address;

means for isolating a selected group of memory cells in each row from the remainder of the row in response to a bulk write signal, including a pair of pass transistors, each having a conductive path and a control terminal, wherein each of the pass transistors has a conductive path between the selected group of memory cells in the row and the remainder of the memory cells in the row, and wherein a first one of the pass transistors has its control terminal connected to the bulk write signal and a second one of the pass transistors has its control terminal connected to the inverse of the bulk write signal; and

means for receiving the bulk write signal in each column of the selected memory cells and writing a first logic state into the selected memory cells in response to the bulk write signal.

13. A memory in an integrated circuit, comprising:

a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein;

a plurality of pairs of bit lines, each associated with one of the columns;

a column decoder for selecting a plurality of columns in the array responsive to a column address;

means for isolating a selected group of memory cells in each row and the remainder of the row in response to a bulk write signal; and

means for receiving the bulk write signal in each column of the selected memory cells and writing a first logic state into the selected memory cells in response to the bulk write signal, such means including a first pull-up transistor connected to a first bit line of its associated bit line pair and a second pull-up transistor connected to a second bit line of its associated bit line pair, and means, connected to a bit line of the bit line pair, for driving the bit line to a selected value in response to the bulk write signal.

14. The memory of claim 13, wherein the means is a first transistor.

15. The memory of claim 14, wherein the first transistor is a pull-down transistor and wherein the first pull-up transistor is turned off, the first pull-down transistor is turned on, and the bit line is pulled low in response to the bulk write signal.