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Selective bulk write operation

  • US 5,311,467 A
  • Filed: 04/07/1992
  • Issued: 05/10/1994
  • Est. Priority Date: 04/07/1992
  • Status: Expired due to Term
First Claim
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1. A memory in an integrated circuit, comprising:

  • a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein;

    a plurality of pairs of bit lines, each associated with one of the columns;

    a column decoder for selecting a plurality of columns in the array responsive to a column address;

    a plurality of word line drivers for selecting, in response to a row address, a row of memory cells wherein each memory cell is connected to its associated pair of bit lines;

    a plurality of row isolation circuits for isolating a selected group of memory cells in each row from the remainder of the row in response to a bulk write signal, each row isolation circuit having a conduction path between the selected memory cells in the associated row and the remainder of the row, wherein each row isolation circuit includes a pass gate having a conductive path and a control terminal for isolating the selected memory cells in each row from the remainder of the row in response to the bulk write signal, and an enable transistor for selecting, in response to a control signal, the selected group of memory cells; and

    means for receiving the bulk write signal in each column of the selected memory cells and writing a first logic state into the selected memory cells in response to the bulk write signal.

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