Semiconductor memory with improved test mode
First Claim
1. An integrated circuit, comprising:
- an array of memory cells arranged in rows and columns;
a row decoder for selecting a row of memory cells responsive to a row address;
a plurality of local data buses;
a column decoder for selecting, in a test mode, a plurality of memory cells in said selected row for communication with said plurality of local data buses;
an output terminal;
an output buffer having a data input, an enable input, and having its output connected to said output terminal, wherein said output buffer presents a high impedance state at said output terminal responsive to receiving a disable signal at its enable input;
a data bus, coupled to one of said plurality of local data buses, for communicating its data state to the data input of said output buffer;
a comparator circuit, having inputs connected to said plurality of local data buses, for comparing the data states on said local data buses to one another, said comparator circuit having an output connected to said enable input of said output buffer and providing said disable signal to said output buffer responsive to the comparison indicating that the data states on said local data buses do not match one another;
wherein said comparator circuit is connected to said local data buses in parallel with said data bus.
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Abstract
An integrated circuit memory is disclosed which has a parallel test read mode. The memory includes comparators for comparing multiple data words, on a bit-by-bit basis, during the parallel read mode, with the result of the comparison used to enable or disable the output buffers. In test mode, in the event of a failed parallel test comparison, the comparator causes the output buffers to go into a high-impedance state; for a passing parallel test, the actual data state is presented by the output terminals. The comparison circuitry is in parallel with the output data path, so that the output data path is not adversely affected by the test circuitry, and so that the access time in test mode is the same as the access time during normal operation (assuming a passing test). The technique may be adapted to wide parallel test schemes.
35 Citations
23 Claims
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1. An integrated circuit, comprising:
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an array of memory cells arranged in rows and columns; a row decoder for selecting a row of memory cells responsive to a row address; a plurality of local data buses; a column decoder for selecting, in a test mode, a plurality of memory cells in said selected row for communication with said plurality of local data buses; an output terminal; an output buffer having a data input, an enable input, and having its output connected to said output terminal, wherein said output buffer presents a high impedance state at said output terminal responsive to receiving a disable signal at its enable input; a data bus, coupled to one of said plurality of local data buses, for communicating its data state to the data input of said output buffer; a comparator circuit, having inputs connected to said plurality of local data buses, for comparing the data states on said local data buses to one another, said comparator circuit having an output connected to said enable input of said output buffer and providing said disable signal to said output buffer responsive to the comparison indicating that the data states on said local data buses do not match one another; wherein said comparator circuit is connected to said local data buses in parallel with said data bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. In an integrated circuit memory having a normal operating mode and a parallel test mode, said memory having an array of memory cells, wherein a memory cell is accessed in said normal operating mode, and wherein a plurality of said memory cells are accessed for comparison of their contents in said parallel test mode, output circuitry comprising:
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an output terminal; an output buffer for driving said output terminal, said output buffer having a data input and an enable input; a data bus connected to said data input of said output buffer; a plurality of local data buses with which accessed memory cells are in communication; a selection circuit for selecting a local data bus for connection to said data bus; a comparison circuit connected, in parallel with said selection circuit, to said plurality of local data buses, for comparing the contents of said local data buses when said memory is in test mode, said comparison circuit having an output connected to the enable input of said output buffer so that, responsive to the contents of said local data buses compared by said comparison circuit not matching one another, said output buffer is disabled. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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Specification