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Semiconductor memory with improved test mode

  • US 5,311,473 A
  • Filed: 06/02/1993
  • Issued: 05/10/1994
  • Est. Priority Date: 07/13/1990
  • Status: Expired due to Term
First Claim
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1. An integrated circuit, comprising:

  • an array of memory cells arranged in rows and columns;

    a row decoder for selecting a row of memory cells responsive to a row address;

    a plurality of local data buses;

    a column decoder for selecting, in a test mode, a plurality of memory cells in said selected row for communication with said plurality of local data buses;

    an output terminal;

    an output buffer having a data input, an enable input, and having its output connected to said output terminal, wherein said output buffer presents a high impedance state at said output terminal responsive to receiving a disable signal at its enable input;

    a data bus, coupled to one of said plurality of local data buses, for communicating its data state to the data input of said output buffer;

    a comparator circuit, having inputs connected to said plurality of local data buses, for comparing the data states on said local data buses to one another, said comparator circuit having an output connected to said enable input of said output buffer and providing said disable signal to said output buffer responsive to the comparison indicating that the data states on said local data buses do not match one another;

    wherein said comparator circuit is connected to said local data buses in parallel with said data bus.

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