Configurable gigabits switch adapter

• US 5,311,509 A
• Filed: 02/06/1992
• Issued: 05/10/1994
• Est. Priority Date: 09/13/1991
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Heddes, Marco, Luijten, Ronald
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US07/832,127
• Time in Patent Office: 824 Days
• Field of Search: 370/60, 370/60.1, 370/82, 370/94.1, 370/99
• US Class Current: 370/397
• CPC Class Codes: H04L 2012/5653 using the ATM adaptation layer [AAL]
• CPC Class Codes: H04L 49/20 Support for services
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3063 Pipelined operation
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/55 Prevention, detection or correction of errors

Abstract

The present invention relates to a data transmission system and concerns a method for transforming user frames into fixed length cells, e.g. ATM (Asynchronous Transfer Mode), such that the fixed length cells can be transported through a cell handling switch fabric (11). A hardware implementation of this method consists of two parts, a transmitter (12.1) and a receiver (13.1), both being part of a switching subsystem (10) comprising a switch fabric (11). The transmitter (12.1) buffers user data and segments them into fixed length cells to be transported through said switch (11). The receiver part (13.1) reassembles user data on reception of these cells.

Claims

1. In a data transmission system, a method for transforming fixed length cells, each cell having a payload, into user frames, each of said fixed length cells being preceded by a fixed size header, the payload and said fixed size header of each of said fixed length cells being processed separately, said method comprising the following steps:

receiving said fixed length cells,

feeding said fixed length cells in parallel into a parallel bus (54),

separating said payload of the fixed length cell from said fixed size header, said payload being transmitted along said parallel bus (54) via a realignment unit (47) to a buffer memory (52),

processing said fixed size header separately to determine a storage address of a storage section in said buffer memory (52),

shifting said payload to the boundary of said parallel bus by means of said re-alignment unit (47),

buffering said payload in said storage section in said buffer memory (52) made accessible by said storage address after being shifted to the bus boundary,

supporting at least one virtual channel by employing a control section corresponding to said virtual channel, said control section comprising queuing means whereby the storage addresses of the storage sections in said buffer memory (52) which have been allocated by said virtual channel are stored, the buffered payload of said virtual channel being accessible by reading said storage addresses from said buffer memory (52).

2. The method of claim 1, wherein said fixed length cell is transformed into a user frame by

processing said fixed size header which has been separated from said payload, while transmitting said payload along said parallel bus (54) and shifting said payload to the boundary of said parallel bus (54), to determine if space for said payload is available in said buffer memory (52), by employing system state variables of said buffer memory (52),

using said determined storage address of a storage section for writing said payload into said storage section of said buffer memory (52) if said space is available,

and wherein user frames are generated, after buffering said payload in said storage section, by

reading said payload from said storage section, using said storage address,

forming a user frame according to a defined data transmission protocol, and

transmitting said user frame.

3. The method of claim 2, wherein said storage address of a storage section is determined after a fixed number of bus cycles such that said payload which has been delayed during these bus cycles, can be stored in the storage section corresponding to said storage address.

4. The method of claim 2, wherein the storage addresses of storage sections are kept in queues such that the payload stored in these storage sections can be retrieved for the generation of said user frames by successively reading the storage addresses of the storage sections from said queues.

5. The method of claim 2, wherein fixed length cells of different priority are supported by storing the storage addresses of the storage sections where the payload of said fixed length cells has been stored in at least one queue such that for the generation of user frames the payload with the highest priority can be taken from the corresponding storage section prior to any payload with lower priority.

6. In a data transmission system, a method for transforming a user frame into a fixed length cell, said fixed length cell being preceded by a fixed size header, the method comprising the steps of:

buffering the payload of said user frame in a storage section of a buffer memory (24'"'"') using a storage address of said storage section,

keeping said storage address in a queue (28.1'"'"', 28.2'"'"') such that said payload can be retrieved from said buffer memory (24'"'"') by taking said storage address from said queue (28.1'"'"', 28.2'"'"'),

generating and processing said fixed size header separately prior to prefixing said payload with said fixed size header,

taking said payload out of said buffer memory (24'"'"') using said corresponding storage address and inserting said payload into a fixed length cell, and

transmitting said fixed length cell consisting of said payload preceded by said fixed size header.

7. The method of claim 6, wherein said user frame is transformed into said fixed length cell by

reading said payload partly from said storage section, accessible using said storage address kept in said queue (28.1'"'"', 28.2'"'"'),

concurrently, i.e. while taking said payload from said storage section, generating said fixed size header,

forming said fixed length cell by insertion of a part of said payload, preceded by said fixed size header, and

transmitting said fixed length cell.

8. The method of claim 7, wherein said payload is read from said storage section by taking its storage address from said queue (28.1'"'"', 28.2'"'"') and the payload is delayed during the generation of said fixed size header which is presented after a fixed number of clock cycles.

9. The method of claim 7, wherein said payload is realigned to a fixed length cell prior to the re-assembly of said fixed length cell such that said payload can be inserted into said fixed length cell directly adjacent to said fixed size header without wasting transmission capacity.

10. The method of claim 7, wherein user frames of different priority are supported by storing the storage addresses of the storage sections where each payload is stored in at least one queue (28.1'"'"', 28.2'"'"') such that for the generation of said fixed length cells the payload with the highest priority can be taken from the storage section where it has been stored by taking the storage address of said storage section from said queue (28.1'"'"', 28.2'"'"') prior to taking the storage address of the storage section of the next payload with lower priority from said queue (28.1'"'"', 28.2'"'"').

11. Apparatus for transforming fixed length cells into user frames, each of said fixed length cells being preceded by a fixed size header, comprising:

means for receiving a fixed length cell and transmitting said fixed length cell in parallel via a parallel bus,

means (23) for separating the payload of said fixed length cell from said fixed size header transmitted via said parallel bus,

header processor (22), connected to said parallel bus, for separately processing said fixed size header, to determine a storage address of a storage section in a buffer memory (24),

re-alignment means for shifting said payload, received via said parallel bus, to the boundary of said parallel bus,

means (23.3, 23.4) for buffering said payload, after said payload has been separated from said fixed size header and has been realigned, until said storage address is available,

means (24,

     26) for storing said payload in a storage section of said buffer memory (24) made accessible by said storage address,

queuing means (25) for keeping said storage address corresponding to said payload in a queue,

means for retrieving said payload from said storage section by successively taking the respective storage addresses from the queue of said queuing means (25),

means for forming said user frame with said retrieved payload, in accordance with a predetermined data transmission protocol, and

means for the transmission of said user frames.

12. The apparatus of claim 11, further comprising queuing means (28.1, 28.2) for supporting the transmission of fixed length cells with different priority by keeping the respective storage address in a queue of said queuing means, such that the payload with highest priority can be retrieved from said storage section of said buffer memory (24) by taking its storage address from said queue prior to any storage address of payload with lower priority.

13. A data transmission network comprising a cell handling switch fabric (11);

and the apparatus of claim 11 for receiving the fixed length cells being routed through said switch fabric and for transforming the received fixed length cells into user frames prior to transmitting them.

14. Apparatus for transforming user frames, each comprising a payload into fixed length cells, each of said fixed length cells being preceded by a fixed size header, the apparatus comprising:

means for buffering the payloads of said user frames in a storage section of a buffer memory (24'"'"'),

queuing means (28.1'"'"', 28.2'"'"') for keeping the storage address of said storage section in a queue being part of said queuing means,

header processor (22'"'"') taking said storage address from the queue of said queuing means (28.1'"'"', 28.2'"'"') and generating a fixed size header,

means for retrieving said payload from said buffer memory (24'"'"') using said storage address taken from said queue,

means for forming said fixed length cell by prefixing a part of said retrieved payload with said header, and

means for transmitting said fixed length cell.

15. The apparatus of claim 14, wherein said header processor (22'"'"') takes a storage address of payload with highest priority from the queue of said queuing means (28.1'"'"', 28.2'"'"') prior to storage addresses of payload with lower priority.

16. The apparatus of claim 14, further comprising a re-align unit (23'"'"') for re-aligning said payload taken from a storage section of said buffer memory (24'"'"') prior to prefixing it with said fixed size header such that said payload can be inserted into said fixed length cell directly adjacent to said fixed size header.

17. A data transmission network comprising a cell handling switch fabric (11);

and the apparatus of claim 14 for transforming user frames into fixed length cells and transmitting the fixed length cells to said switch fabric (11).