Global planarization using SOG and CMP

• US 5,312,512 A
• Filed: 10/23/1992
• Issued: 05/17/1994
• Est. Priority Date: 10/23/1992
• Status: Expired due to Term

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: NCR Corporation
• Inventors: Fuchs, Kenneth P., Allman, Derryl D. J.
• Primary Examiner(s): Bueker, Richard
• Assistant Examiner(s): Fleck, Linda J.
• Application Number:
  US07/965,309
• Time in Patent Office: 571 Days
• Field of Search: 437/231, 437/228, 156/636
• US Class Current: 438/624
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/316 composed of oxides or glassy oxides or oxide based glass
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051

Abstract

A method for planarizing the surface of a semiconductor device which employs spin on glass (SOG) and an etching operation to remove high portions of the SOG prior to a chemical metal polish (CMP) operation. The SOG is baked and cured before etching. Additional layers of SOG and etching operations may be employed as necessary. A thick encapsulating oxide layer is deposited over the SOG layer. For surface irregularities caused by metal lines, an insulating layer may be deposited over the surface before the SOG. Where an additional metal line is to be deposited on the surface, an additional insulating layer is deposited after the CMP operation. In the case of metal lines made of aluminum, provision is also made for preventing Hillock formations on the metal lines.

Claims

1. A method of planarizing a semiconductor device having an irregular surface with high and low portions, wherein the semiconductor device has a plurality of aluminum metal lines causing the irregular surface, the method comprising the steps of:

depositing a PECVD siloxane ILD layer over the surface;

spinning a layer of SOG over the ILD layer;

heating the SOG layer to drive out solvents and low-boiling point organics, including the substep of performing a hot plate process at temperatures between about 50 to 300 degrees Celsius for about one second to five minutes;

curing the SOG layer;

etching away higher portions of the SOG layer;

depositing an oxide filling layer over the SOG layer;

perform a mask and etch operation to form holes through the oxide filling layer and the SOG layer down to the metal lines;

depositing plugs into the holes and in contact with the metal lines, wherein the plugs are tungsten to prevent hillock formations;

performing a CMP operation to smooth the oxide filling layer; and

depositing another aluminum metal line over the oxide filling layer and in contact with the tungsten plugs.

2. A method of planarizing a semiconductor device having an irregular surface with high and low portions, wherein the semiconductor device has a plurality of metal lines causing the irregular surface, the method comprising the steps of:

depositing a PECVD siloxane ILD layer over the surface;

spinning a layer of SOG over the ILD layer;

heating the SOG layer to drive out solvents and low-boiling point organics, including a substep of performing a hot plate process at temperatures between about 50 to 300 degrees Celsius for about one second to five minutes;

curing the SOG layer;

etching away higher portions of the SOG layer;

depositing an oxide filling layer over the SOG layer which fills voids between the metal lines, wherein the oxide filling layer extends from the SOG layer to about 5000 angstroms to 2 microns above the metal lines;

performing a CMP operation to smooth the oxide filling layer;

depositing a second PECVD siloxane ILD layer over the smoothed oxide filling layer; and

depositing another metal line over the second ILD layer.