Integrated process for fabricating raised, source/drain, short-channel transistors

• US 5,312,768 A
• Filed: 03/09/1993
• Issued: 05/17/1994
• Est. Priority Date: 03/09/1993
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gonzalez, Fernando
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): TSAI, H JEY
• Application Number:
  US08/028,311
• Time in Patent Office: 434 Days
• Field of Search: 437/52, 437/60, 437/919, 437/41, 437/44, 437/40, 437/34
• US Class Current: 438/227
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

Processes for fabrication of: an N-channel raised source/drain MOSFET transistor; an N-channel and P-channel raised source/drain MOSFET device; and an N-channel raised source/drain MOSFET in conjunction with a DRAM memory cell capacitor. The process deposits a layer of titanium nitride over the N-channel and P-channel source/drain areas which acts as a barrier to phosphorus or boron atom outdiffusion so that the junction doping levels remain low in the source/ drain areas, and N-channel and P-channel junctions will be shallow. The titanium nitride layer will serve as a dopant atom barrier in a capacitor storage node, an N-channel source/drain area, and a P-channel source/drain area.

Claims

1. In a partially completed, N-channel MOSFET device having a gate structure, a pair of oxide spacers adjacent the gate structure, a pair of silicon nitride barrier spacers adjacent the oxide spacers, a doped source and drain area over a P-well in a substrate, and a field oxide layer adjacent the source and drain area, a process for completing fabrication of a raised source/drain N-channel MOSFET device comprising the steps of:

a growing a second field oxide layer over the source and drain areas;

b. selectively etching the silicon nitride barrier spacers, thereby exposing a narrow source and drain area between the oxide spacer and the second field oxide layer;

c. depositing a transition metal nitride layer over the MOSFET device;

d. depositing a polysilicon layer over the metal nitride layer; and

simultaneously

e. in situ doping the polysilicon layer to create a conducting polysilicon layer, wherein the transition metal nitride layer acts as a barrier to ion migration to the source and drain areas;

f. etching the polysilicon layer to form an opening over the gate structure and a boundary over the field oxide layer wherein the metal nitride layer acts as an etch barrier;

g. etching the transition metal nitride layer to form openings over the gate structure and a boundary over the field oxide layer, thereby forming a raised source/drain electrical connection;

h. depositing an oxide isolation layer over the MOSFET device;

i. patterning and etching a pair of contact openings in the oxide isolation layer over the conducting polysilicon wherein the nitride layer acts as an etch barrier;

j. depositing a thin titanium nitride layer within the contact openings;

k. depositing and patterning a metal conductor within the contact opening; and

then

l. depositing and patterning a pair of bit line metal conductors over the metal conductor in the contact opening thereby providing a low-resistance electrical connection from the bit line through the raised source/drain electrical connection to the narrow source and drain areas.

2. The raised source/drain MOSFET fabrication process as recited in claim 1 wherein the transition metal is selected from the group consisting of tungsten, molybdenum, tantalum, titanium, platinum, and cobalt.

3. The raised source/drain MOSFET fabrication process as recited in claim 1 wherein the transition metal nitride is titanium nitride.

4. The raised source/drain MOSFET fabrication process as recited in claim 3 wherein the polysilicon layer is in situ doped with phosphorous or arsenic.

5. In a partially completed, N-channel MOSFET device having a gate structure, a pair of oxide spacers adjacent the gate structure, a pair of silicon nitride barrier spacers adjacent the oxide spacers, a doped source and drain area over a P-well in a substrate, and a field oxide layer adjacent the source and drain area, a process for completing fabrication of a raised source/drain N-channel MOSFET device comprising the steps of:

a. growing a second field oxide layer over the source and drain areas;

b. selectively etching the silicon nitride barrier spacers, thereby exposing a narrow source and drain area between the oxide spacer and the second field oxide layer;

c. depositing a titanium nitride layer over the MOSFET device;

d. depositing a polysilicon layer over the titanium nitride layer;

e. in situ doping the polysilicon layer with phosphorous or arsenic to create a conducting polysilicon layer, wherein the titanium nitride layer acts as a barrier to ion migration to the source and drain areas;

f. etching the polysilicon layer to form an opening over the gate structure and a boundary over the field oxide layer wherein the titanium nitride layer acts as an etch barrier;

g. etching the titanium nitride layer to form openings over the gate structure and a boundary over the field oxide layer, thereby forming a raised source/drain electrical connection;

h. depositing an oxide isolation layer over the MOSFET device;

i. patterning and etching a pair of contact openings in the oxide isolation layer over the conducting polysilicon;

j. depositing a thin titanium nitride layer within the contact openings;

k. depositing and patterning a tungsten conductor within the contact opening; and

then

l. depositing and patterning a pair of aluminum bit lines over the tungsten in the contact openings thereby providing a low-resistance electrical connection from the bit line through the raised source/drain electrical connection to the narrow source and drain areas wherein the distance between the pair of bit lines is greater than the distance between the narrow source/drain areas.

6. In a semiconductor device, an integrated process for fabrication of both an N-channel MOSFET device and a P-channel MOSFET device on a substrate comprising the steps of:

a. depositing sequentially over the semiconductor surface a thin gate oxide layer, a polysilicon layer, a refractory metal silicide layer, and a top layer oxide;

b. patterning a gate structure over an N-channel area;

c. implanting ions in a source and drain area adjacent the N-channel gate structure;

d. patterning a barrier spacer on opposite sides of the N-channel gate structure;

e. growing a field oxide adjacent the N-channel gate structure over the substrate wherein the field oxide is bounded by the barrier spacer;

f. etching to selectively remove the barrier spacer thereby exposing the source and drain areas;

g. depositing a photoresist layer over the N-channel and P-channel devices;

h. patterning a P-channel gate structure while protecting the N-channel device with the photoresist layer;

i. ion implanting a low-dose P-channel source and drain area;

j. forming an oxide spacer on opposite sides of the N-channel and P-channel gate structures;

k. depositing a titanium nitride layer over the N-channel and P-channel devices;

l. depositing a polysilicon layer over the N-channel and P-channel devices;

m. in situ doping the polysilicon layer to create a conducting polysilicon layer;

n. selectively etching the conducting polysilicon layer over the N-channel and P-channel devices to form an opening over the N-channel and P-channel gate structures and a boundary over the field oxide layer of the N-channel and P-channel devices;

o. selectively etching the titanium nitride layer to form openings over the N-channel and P-channel gate structures and a boundary over the field oxide layers thereby forming a raised source/drain electrical connection at the N-channel and P-channel devices;

p. depositing an oxide isolation layer over the MOSFET device;

q. patterning a plurality of contact openings in the oxide isolation layer over the conducting polysilicon of the N-channel and P-channel devices;

r. depositing a thin titanium nitride layer within the contact openings;

s. depositing and patterning a tungsten conductor within the plurality contact openings; and

then

t. depositing and patterning a plurality of bit line metal conductors over the metal conductor in the contact opening thereby providing a low-resistance electrical connection from the bit line through the raised source/drain electrical connection to the source and drain areas of both N-channel and P-channel devices.

7. The integrated process for fabrication as recited in claim 6 wherein the polysilicon layers are in situ doped by phosphorus or arsenic.

8. The integrated process for fabrication as recited in claim 7 wherein the P-channel source and drain areas are doped by a phosphorous halo implant and a boron implant.

9. The integrated process for fabrication as recited in claim 8 wherein the N-channel source and drain are doped by a boron and phosphorous implant.