Semiconductor device for minimizing diffusion of conductivity enhancing impurities from one region of a polysilicon layer to another

• US 5,313,087 A
• Filed: 09/30/1993
• Issued: 05/17/1994
• Est. Priority Date: 08/30/1991
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Shih, Bohr-Winn, Fazan, Pierre C., Chan, Hiang C.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): SAADAT, MAHSHID D
• Application Number:
  US08/129,872
• Time in Patent Office: 229 Days
• Field of Search: 257/58, 257/62, 257/379, 257/380, 257/381, 257/385, 257/536-538, 257/656, 365/154, 365/156, 365/175, 365/178, 365/181
• US Class Current: 257/538
• CPC Class Codes: H01L 21/32155 Doping polycristalline - or amorphous silicon layers
• CPC Class Codes: H01L 28/20 Resistors

Abstract

A polysilicon layer is provided with a p-type impurity, and masked with an oxide mask to define a p-type region of the polysilicon layer. A second impurity is then provided into first unmasked regions of the polysilicon layer. A second oxide mask is deposited and anisotropically etched to form spacers adjacent to the first oxide mask. The spacers define two diffusion barrier regions of the polysilicon layer adjacent to the p-type region. An n-type impurity is then provided into second unmasked regions of the polysilicon layer to form two n-type regions adjacent the diffusion barrier regions. The diffusion barrier regions prevent cross diffusion of the p-type and the n-type impurities within the polysilicon layer, while also being of sufficient dimensions to permit normal p/n operations.

Claims

1. A back-to-back diode resistor comprising:

a polysilicon layer having two n-type regions separated by a p-type region, the polysilicon layer having interfaces between the p-type region and each of the n-type regions; and

a diffusion barrier region disposed at each of the interfaces between the p-type region and the two n-type regions, the diffusion barrier regions having a selected width and containing a diffusion inhibiting impurity at a selected concentration, the p-type region being substantially void of the diffusion inhibiting impurity.

2. A back-to-back diode resistor according to claim 1 wherein the diffusion inhibiting impurity is selected from the group consisting of nitrogen, oxygen, and germanium.

3. A back-to-back diode resistor according to claim 1 wherein each of the diffusion barrier regions has a width of approximately 500 to approximately 3000 Angstroms.

4. A back-to-back diode resistor according to claim 1 wherein the diffusion inhibiting impurity is selected from the group consisting of nitrogen, oxygen, and germanium;

and each of the diffusion barrier regions has a width of approximately 500 to approximately 3000 Angstroms.

5. A back-to-back diode resistor according to claim 1 wherein the diffusion inhibiting impurity is selected from the group consisting of nitrogen, oxygen, and germanium;

and each of the diffusion barrier regions has a width of approximately 1000 Angstroms.

6. A back-to-back diode resistor according to claim 1 whereby the back-to-back diode resistor is approximately 2 microns or less in length.

7. An SRAM incorporating the back-to-back diode resistor of claim 1.

8. A semiconductor device comprising a polysilicon layer having first, second, and third regions, the second region being disposed between the first and third regions, the semiconductor device further comprising diffusion barrier regions of a predetermined width between the first and second regions and between the second and third regions, the second region being provided with a first impurity of a first conductivity type to a first concentration, the diffusion barrier regions being provided with a second impurity to a second concentration, and the first and third regions being provided with a third impurity of a second conductivity type opposite the first conductivity type, the first and third regions being provided to a third concentration greater than the first concentration.

9. An SRAM memory device comprising:

a first transistor having a source coupled to ground, a drain and a gate;

a second transistor having a source coupled to ground, a drain coupled to the gate of the first transistor, and a gate coupled to the drain of the first transistor;

a third transistor having a source coupled to a first bit line, a drain connected to the drain of the first transistor, and a gate connected to a word line;

a fourth transistor having a source coupled to a second bit line, a drain connected to the drain of the second transistor, and a gate connected to the word line;

a first resistive element coupled between the drain of the first transistor and a power source; and

a second resistive element coupled between the drain of the second transistor and the power source;

the first and second resistive elements being formed in a polysilicon layer, the polysilicon layer comprising;

two n-type regions separated by a p-type region, the polysilicon layer having interfaces between the p-type region and each of the n-type regions; and

a diffusion barrier region disposed at each of the interfaces between the p-type region and the two n-type regions, the diffusion barrier regions having a selected width and containing a diffusion inhibiting at a selected concentration, the p-type region being substantially void of the diffusion inhibiting impurity.