IC chip package having chip attached to and wire bonded within an overlying substrate

• US 5,313,096 A
• Filed: 07/29/1992
• Issued: 05/17/1994
• Est. Priority Date: 03/16/1992
• Status: Expired due to Fees

• Current Assignee: Staktek Group L.P. (Entorian Technologies)
• Original Assignee: Dense-Pac Microsystems Incorporated
• Inventors: Eide, Floyd K.
• Primary Examiner(s): Mintel, William
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US07/920,763
• Time in Patent Office: 657 Days
• Field of Search: 257/784, 257/778, 257/686, 257/685, 257/621, 257/774, 361/393
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48237 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1064 Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H05K 13/0465 by soldering H05K13/0469 takes precedence

Abstract

An IC chip package includes a chip having an upper active surface thereof bonded to the lower surface of a substrate. A plurality of terminals on the active surface are wire bonded within the outer periphery of the chip by bonding wires extending through a plurality of apertures in a lower layer of the substrate to bonding pads on an upper surface of the lower substrate layer. Metallized strips couple the bonding pads to conductive pads at the outer edges of the lower substrate layer. The substrate includes an upper layer having apertures therein. After wire bonding, the apertures in the upper and lower substrate layers are filled with epoxy which is cured and then ground flush with the upper surface of the upper substrate layer. The chip is then lapped to a desired thickness, following which the chip package is electrically tested at various temperatures. The chip package is programmed by wire bonding a chip enable trace to one of a plurality of optional bonding pads of a bonding option array on the lower substrate layer, following which an aperture within the upper substrate layer which provides access to the bonding option array is filled with epoxy which is then cured and ground flat at the upper surface of the substrate. The chip package may then be assembled together with other chip packages into a stack, with the conductive pads of the substrates being joined by strip soldering to form vertical conductive columns.

Claims

1. A chip package comprising the combination of:

a chip having a plurality of terminals on an active surface thereof;

a lower substrate layer having opposite upper and lower surfaces and at least one aperture extending between the upper and lower surfaces and a plurality of bonding pads on the upper surface, the lower surface of the lower substrate being coupled to the active surface of the chip;

a plurality of bonding wires, each extending through the at least one aperture in the lower substrate layer and coupling one of the plurality of terminals on the active surface of the chip to one of the plurality of bonding pads on the upper surface of the lower substrate layer; and

an upper substrate layer disposed on the upper surface of the lower substrate layer, the upper substrate layer having at least one aperture therein communicating with the at least one aperture in the lower substrate layer.

2. A chip package in accordance with claim 1, wherein the at least one aperture in the upper substrate layer and the at least one aperture in the lower substrate layer are filled with epoxy.

3. A chip package in accordance with claim 1, wherein the lower substrate layer has a plurality of conductive pads on an outer periphery of the upper surface thereof coupled to the plurality of bonding pads on the upper surface by metallized strips.

4. A chip package in accordance with claim 3, wherein the lower substrate layer and the upper substrate layer together define a plurality of outer edges of the chip package, and further including a plurality of conductive elements mounted on at least one of the plurality of outer edges of the chip package and coupled to the plurality of conductive pads on the lower substrate layer.

5. A chip package in accordance with claim 1, wherein the plurality of terminals on the active surface of the chip are divided into first and second groups of terminals adjacent opposite ends of the chip, the lower substrate layer has two apertures therein disposed over the first and second groups of terminals respectively on the chip, and the plurality of bonding pads on the upper surface of the lower substrate layer are divided into first and second groups of bonding pads adjacent the first and second apertures respectively in the lower substrate layer.

6. A chip package in accordance with claim 5, wherein the upper substrate layer has first and second apertures therein disposed over and larger in size than the first and second apertures respectively in the lower substrate layer.

7. A chip package in accordance with claim 6, wherein the upper substrate layer has a relatively flat upper surface and the first and second apertures in the lower substrate layer and the first and second apertures in the upper substrate layer are filled with epoxy which is ground flat and continuous with the upper surface of the upper substrate layer.

8. A chip package in accordance with claim 1, further including a bonding option array disposed on the upper surface of the lower substrate layer and including a central terminal coupled to one of the plurality of bonding pads, a plurality of optional bonding pads and a bonding wire coupling the central terminal to one of the plurality of optional bonding pads.

9. A chip package in accordance with claim 8, wherein the upper substrate layer has an aperture therein disposed over the bonding option array.

10. A chip package in accordance with claim 9, wherein the upper substrate layer has a relatively flat upper surface and the aperture in the upper substrate layer is filled with epoxy which is ground flat and continuous with the upper surface of the upper substrate layer.

11. A stack of chip packages comprising the combination of:

a base;

a stack of chip packages mounted on the base and each of the chip packages having a plurality of conductors at an outer periphery thereof coupled to a plurality of conductors on the other chip packages by a plurality of vertical conductors; and

each of the chip packages comprising a chip of relatively thin, generally planar configuration bonded to an underside of a substrate of generally planar configuration and having a plurality of electrical terminals wire bonded within the chip package to a plurality of electrical terminals within the substrate, the chip of at least some of the chip packages having a surface coupled to a surface of the substrate of an adjacent chip package.

12. A stack of chip packages in accordance with claim 11, wherein each chip package includes a lower substrate layer bonded to the chip and having the plurality of electrical terminals on an upper surface thereof adjacent at least one aperture therein, and the plurality of electrical terminals on the chip are bonded to the plurality of electrical terminals on the upper surface of the lower substrate layer by bonding wires extending through the at least one aperture in the lower substrate layer.

13. A chip package comprising the combination of:

a chip having a plurality of terminals on a surface thereof;

a substrate having opposite first and second surfaces, an aperture therein extending between the first and second surfaces, and a plurality of terminals disposed within the aperture, the second surface of the substrate being coupled to the surface of the chip so that the plurality of terminals on the surface of the chip are disposed within the aperture in the substrate;

a plurality of bonding wires disposed within the aperture in the substrate and coupling the plurality of terminals disposed within the aperture to the plurality of terminals on the surface of the chip; and

filling material disposed within and filling the aperture in the substrate.

14. A chip package in accordance with claim 13, further including a plurality of conductors disposed within the substrate and coupling the plurality of terminals disposed within the aperture to an external surface of the substrate.

15. A chip package in accordance with claim 13, wherein the aperture has a surface generally parallel to the first and second surfaces of the substrate on which the plurality of terminals disposed within the aperture are mounted.

16. A chip package in accordance with claim 13, wherein the first surface of the substrate is relatively flat and the filling material comprises epoxy which has a flat upper surface generally continuous with the first surface of the substrate.

17. A chip package in accordance with claim 13, wherein the substrate has a second aperture extending into the substrate from the first surface thereof, and further including a bonding option array of conductors mounted within the aperture, a bonding wire disposed within the second aperture and coupling selected conductors of the bonding option array, and filling material disposed within and filling the second aperture in the substrate.

18. A chip package in accordance with claim 13, wherein the substrate is comprised of a first layer of thin, planar configuration having opposite first and second surfaces, with the second surface thereof defining the second surface of the substrate, and an aperture extending between the opposite first and second surfaces thereof and forming a part of the aperture of the substrate, the plurality of terminals disposed within the aperture of the substrate being mounted on the first surface of the first layer, a plurality of conductors mounted on the first surface of the first layer and extending between the plurality of terminals and an external surface of the substrate, and a second layer of thin, planar configuration having opposite first and second surfaces, with the first surface thereof defining the first surface of the substrate and the second surface thereof coupled to the first surface of the first layer, the second layer having an aperture extending between the opposite first and second surfaces thereof and forming a part of the aperture of the substrate.

19. A chip package in accordance with claim 18, wherein the second layer has a second aperture extending between the opposite first and second surfaces thereof, and spaced apart from the first-mentioned aperture in the second layer, and further including a bonding option array of conductors mounted on the first surface of the first layer within the second aperture in the second layer, a bonding wire disposed within the second aperture in the second layer and coupling selected conductors of the bonding option array, and filler material disposed within and filling the second aperture in the second layer.