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Packaging arrangement for power semiconductor devices

  • US 5,313,098 A
  • Filed: 04/08/1993
  • Issued: 05/17/1994
  • Est. Priority Date: 04/08/1993
  • Status: Expired due to Term
First Claim
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1. A packaging arrangement for power semiconductor devices, comprising:

  • a unitary case having two sides, each of said sides having two opposite surfaces;

    one of the two opposite surfaces of each of the two sides having a wall secured thereto and extending continuously and peripherally therearound, said wall defining a heat sink on said one surface;

    the other of the opposite surfaces of each of the two sides including longitudinally extending integral cooling fins;

    at least two slots extending transversely across the longitudinally extending integral cooling fins on the other of the opposite surfaces of each of the two sides for providing cooling fluid turbulence;

    the two sides arranged so that the integral cooling fins on the other of the opposite surfaces of each of the two sides cooperate to provide an integral fin arrangement;

    each of the heat sinks on the one of the two opposite surfaces of each of the two sides having mounted thereto a plurality of substrates with a conductor mounted to each of the substrates;

    power semiconductor devices disposed on the conductors so as to be conductively interconnected through said conductors;

    each of the two sides of the case closed by a lid for hermetically sealing the case; and

    a side of one of the walls on the one of the two opposite surfaces of one of the two sides having feedthrough holes for accepting feedthroughs connected to said power semiconductor devices.

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