Aspect ratio control for picture overlays

• US 5,313,303 A
• Filed: 10/26/1992
• Issued: 05/17/1994
• Est. Priority Date: 06/01/1990
• Status: Expired due to Term

• Current Assignee: Thomson Consumer Electronics Incorporated (Vantiva SA)
• Original Assignee: Thomson Consumer Electronics Incorporated (Vantiva SA)
• Inventors: Saeger, Timothy W., Ersoz, Nathaniel H.
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): HSIA, SHERRIE Y
• Application Number:
  US07/938,224
• Time in Patent Office: 568 Days
• Field of Search: 358/183, 358/182, 358/180, 358/22
• US Class Current: 348/439.1
• CPC Class Codes: H04N 3/223 Controlling dimensions by maintaining the cathode-ray tube high voltage constant H04N3/185
• CPC Class Codes: H04N 3/27 Circuits special to multi-standard receivers
• CPC Class Codes: H04N 5/45 Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 7/007 Systems with supplementary picture signal insertion during a portion of the active part of a television signal, e.g. during top and bottom lines in a HDTV letter-box system
• CPC Class Codes: H04N 7/01 Conversion of standards , e.g. involving analogue television standards or digital television standards processed at pixel level
• CPC Class Codes: H04N 7/0105 using a storage device with different write and read speed
• CPC Class Codes: H04N 7/0122 the input and the output signals having different aspect ratios
• CPC Class Codes: H04N 9/641 Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: Y10S 348/913 Letterbox, e.g. display 16:9 aspect ratio image on 4:3 screen

Abstract

A picture overlay system assures proper image aspect ratios for picture overlays. The system comprises a video memory and a control circuit for writing and reading information from a video signal into and out of the video memory, the information relating to video data. A reading circuit supplies information from the video memory synchronously with a display for another video signal. An interpolator selectively compresses and expands the information read from the reading circuit, independently of any other processing which might vertically compress or expand said video data. A multiplexer combines the video signals for simultaneous display. The reading circuit can comprise an asynchronous line memory for the information read from the video memory, having a write port operable synchronously with the reading of the video memory and a read port operable synchronously with the display for the other video signal.

Claims

1. A display system, comprising:

a video memory;

means for writing and reading video data information from a first video signal into and out of said video memory;

means for supplying said information from said video memory synchronously with a display means for a second video signal; and

,

an interpolator for selectively horizontally compressing and expanding said video data information of said first video signal read from said video memory independently of any vertical compression or expansion of said second video signal, which might also vertically compress or expand said video data information of said first video signal.

2. The system of claim 1, further comprising means for multiplexing said video signals for simultaneous display.

10. The system of claim 1, wherein said supplying means comprises a line memory.

3. A display system comprising:

a video memory;

means for writing and reading video data information from a video signal into and out of said video memory;

a line memory for supplying said information from said video memory, having a write port operable synchronously with said reading of said video memory and a read port operable synchronously with a display means for another video signal; and

an interpolator for selectively horizontally compressing and expanding said information read from said video memory independently of any other processing which might vertically compress or expand said video data information.

4. The system of claim 3, wherein said line memory is asynchronous.

5. The system of claim 3, further comprising means for multiplexing said video signals for simultaneous display.

6. A display system, comprising:

a video memory;

means for writing and reading video data information from a first video signal into and out of said video memory;

means for supplying said information from said video memory synchronously with means for generating a raster for displaying a second video signal; and

,

an interpolator for selectively horizontally compressing and expanding said video data information of said first video signal read from said video memory independently of any vertical compression or expansion of said raster which might also vertically compress or expand said video data information of said first video signal.

7. The system of claim 6, further comprising means for multiplexing said video signals for simultaneous display.

8. The system of claim 6, wherein said supplying means comprises a line memory.

9. The system of claim 8, wherein said line memory is asynchronous.