Three-terminal switched mode power supply integrated circuit

• US 5,313,381 A
• Filed: 09/01/1992
• Issued: 05/17/1994
• Est. Priority Date: 09/01/1992
• Status: Expired due to Term

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Balakrishnan, Balu
• Primary Examiner(s): Sterrett, Jeffrey L.
• Application Number:
  US07/938,704
• Time in Patent Office: 623 Days
• Field of Search: 363/20, 363/21, 363/97, 363/131, 363/147
• US Class Current: 363/147
• CPC Class Codes: H02M 1/0006 Arrangements for supplying an adequate voltage to the control circuit of converters
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence

Abstract

An embodiment of the present invention is a three-terminal switched mode power supply chip with a signal terminal for accepting a combination of a feedback control signal and bias supply voltage to operate the chip. A feedback extraction circuit separates the feedback signal from the power supply voltage within the chip by sensing the excess current flowing through a shunt regulator.

Claims

1. A switched-mode power supply chip having exactly three electrical connections, comprising:

a first electrical connection terminal providing for a connection to a first end of a primary winding of a transformer with a second end of said primary winding connected to a source of direct current (DC) power;

a second electrical connection terminal providing for a ground reference for said source of DC power;

a third electrical connection terminal providing for a connection to a source of feedback current derived from a secondary winding of said transformer with a second end of said secondary winding connected to said ground reference for said source of DC power, wherein a combined feedback signal (Ifb) and internal low voltage supply current (Is) may be accepted on a single pin of said chip, such that said low voltage supply current may provide the operating power necessary for voltage regulation after a startup phase and during an operation phase of said chip;

a junction-type field effect transistor (JFET) having a drain electrode connected to the first electrical connection terminal, a gate electrode connected to the second electrical connection terminal, and a source electrode for providing a bias voltage that is reduced substantially from a voltage appearing at the first electrical connection terminal;

a metal oxide semiconductor field effect transistor (MOSFET) having a drain electrode connected to said source electrode of the JFET and thereby placing the MOSFET and JFET in series connection, a gate electrode for controlling a switching current through both the JFET and MOSFET in series, and a source electrode connected to the second electrical connection terminal;

voltage regulation means having an input connected to the third electrical connection terminal and an output connected to said gate of the MOSFET and having a bias voltage power supply connection to said source electrode of the JFET for switching the MOSFET and JFET on and off according to a feedback current received at the third electrical connection terminal, wherein a voltage output by said transformer is thereby regulated; and

input means connected to the third electrical connection terminal for accepting a combined feedback signal (Ifb) and internal low voltage supply current (Is) on a single pin, wherein said low voltage supply current provides operating power for the voltage regulation means after said startup and during said operation of said chip.

2. A semiconductor chip having as few as three external electrical connections, comprising:

a first electrical connection terminal providing for a pulse-width modulated output relative to an internal ground reference;

a second electrical connection terminal providing for connection of said internal ground reference to an external ground reference;

a third electrical connection terminal providing for a connection to a combined source of bias supply power and a feedback current that is controlled in part by said pulse-width modulated output;

voltage regulation means having an input connected to the third electrical connection terminal and an output connected to control the on and off duty cycle of an output transistor connected between the first and second electrical connection terminals according to said feedback current received at the third electrical connection terminal, wherein an output of a circuit including said chip is thereby regulated; and

input means connected to the third electrical connection terminal for accepting a combined feedback signal (Ifb) and internal low voltage supply current (Is) on a single pin for providing operating power with said low voltage supply current to the voltage regulation means after a startup and during operation of said chip.

3. The chip of claim 2, further comprising:

a first transistor having a drain electrode connected to the first electrical connection terminal, a gate electrode connected to the second electrical connection terminal, and a source electrode for providing a bias voltage that is reduced substantially from a voltage appearing at the first electrical connection terminal; and

a second transistor having a drain electrode connected to said source electrode of the first transistor and thereby placing the second transistor and first transistor in series connection, a gate electrode for controlling a switching current through both the first transistor and second transistor in series, and a source electrode connected to the second electrical connection terminal.

4. A switched-mode power supply chip having as few as three electrical connections, comprising:

a first electrical connection terminal providing for a connection to a first end of a primary winding of a transformer with a second end of said primary winding connected to receive a source of direct current (DC) power;

a second electrical connection terminal providing for a ground reference for said source of DC power;

a third electrical connection terminal providing for a connection to a sourced of feedback current derived from a secondary winding of said transformer with a second end of said secondary winding connected to said ground reference for said source of DC power;

voltage regulation means having an input connected to the third electrical connection terminal and an output connected to control an output transistor connected between the first and second electrical connection terminals on and off according to a feedback current received a the third electrical connection terminal, wherein a voltage output by said transformer is thereby regulated and the voltage regulation means is provided with a bias voltage power supply current during operation of said chip; and

input means connected to the third electrical connection terminal for accepting a combined feedback signal (Ifb) and internal low voltage supply current (Is) on a single pin, wherein said low voltage supply current provides operating power for the voltage regulation means after said startup and during said operation of said chip.

5. The chip of claim 4, further comprising:

a first transistor having a drain electrode connected to the first electrical connection terminal, a gate electrode connected to the second electrical connection terminal, and a source electrode for providing a bias voltage to the voltage regulation means that is reduced substantially from a voltage appearing at the first electrical connection terminal; and

a second transistor having a drain electrode connected to said source electrode of the first transistor and thereby placing the second transistor and first transistor in series connection, a gate electrode for controlling a switching current through both the first transistor and second transistor in series, and a source electrode connected to the second electrical connection terminal.

6. The chip of claim 5, wherein:

the first transistor is a junction-type field effect transistor (JFET);

the second transistor is a metal oxide semiconductor field effect transistor (MOSFET); and

the voltage regulation means comprises a pulse width modulator.

7. The chip of claim 4, wherein:

the voltage regulation means further comprises a feedback extractor for separating said feedback signal (Ifb) from said internal low voltage supply current (Is), a Vs regulator and switching-noise filter for separating said feedback signal (Ifb) from said internal low voltage supply current (Is) and then stabilizing it for use by the voltage regulation means.

8. The chip of claim 7, wherein:

the voltage regulation means further includes a high-voltage startup regulator connected to the first electrical connection terminal for providing for a controlled voltage power supply source to the remaining parts of the voltage regulation means during said startup of said chip.

9. The chip of claim 7, wherein:

the voltage regulation means and said feedback extractor include means for monitoring whether there is a sufficient supply current being input to the third electrical connection terminal such that said voltage Vs may be in regulation and that provides for a shunting of an excess current to ground and a mirroring and a converting said shunted excess current to produce an extracted feedback voltage (Vfb).

10. A power supply, comprising:

a three-terminal switched-mode power supply chip, including;

a first electrical connection terminal providing for a connection to a first end of a primary winding of a transformer with a second end of said primary winding connected to receive a source of direct current (DC) power;

a second electrical connection terminal providing for a ground reference for said source of DC power;

a third electrical connection terminal providing for a connection to a source of feedback current derived from a secondary winding of said transformer with a second end of said secondary winding connected to said ground reference for said source of DC power;

voltage regulation means having an input connected to the third electrical connection terminal and an output connected to control an output transistor connected between the first and second electrical connection terminals on and off according to a feedback current received at the third electrical connection terminal for regulating a voltage output by said transformer and for providing the voltage regulation means with a bias voltage power supply current during operation of said chip; and

input means connected to the third electrical connection terminal for accepting a combined feedback signal (Ifb) and internal low voltage supply current (Is) on a single pin, wherein said low voltage supply current provides operating power for the voltage regulation means after said startup and during said operation of said chip;

a transformer, including a primary winding and a secondary winding, connected at a first end of said primary winding to said first electrical connection terminal of the switched-mode power supply chip, and connected at a second end of said primary winding to receive a source of direct current (DC) power;

DC output means for converting an output of a said secondary winding of the transformer to a regulated DC output voltage; and

bias means for converting a voltage induced in said secondary winding of the transformer to a bias supply and connected to said third electrical connection terminal to power the switched-mode power supply chip.

11. The power supply of claim 10, wherein:

the power supply chip further includes;

a first transistor having a drain electrode connected to the first electrical connection terminal, a gate electrode connected to the second electrical connection terminal, and a source electrode for providing a bias voltage that is reduced substantially from a voltage appearing at the first electrical connection terminal; and

a second transistor having a drain electrode connected to said source electrode of the first transistor and thereby placing the second transistor and first transistor in series connection, a gate electrode for controlling a switching current through both the first transistor and second transistor in series, and a source electrode connected to the second electrical connection terminal.