EEPROM with split gate source side injection

• US 5,313,421 A
• Filed: 01/14/1992
• Issued: 05/17/1994
• Est. Priority Date: 01/14/1992
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SunDisk Corporation (Seagate Technology Holdings Plc)
• Inventors: Harrai, Eliyahou, Guterman, Daniel C., Fong, Yupin K., Samachisa, Gheorghe
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Nguyen, Viet Q.
• Application Number:
  US07/820,364
• Time in Patent Office: 854 Days
• Field of Search: 365/182, 365/185, 365/184, 365/218
• US Class Current: 365/185.15
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.

Claims

1. A memory structure comprising:

a source region of a first conductivity type;

a drain region of said first conductivity type;

a first channel region of a second conductivity type opposite said first conductivity type, located adjacent said source region;

a second channel region of said second conductivity type, located between said drain region and said first channel region;

a floating gate located above said second channel region;

a first control gate located above said floating gate, serving as a steering element for a memory transistor;

a second control gate located above said first channel region, serving as a control gate of an access transistor;

a tunneling zone formed between said floating gate and said second control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said floating gate; and

a portion of said second channel region adjacent said drain region, said portion being doped to said second conductivity type to a dopant concentration greater than that of said second channel region.

11. A memory structure as in claims 1, 4, 6, 8, 2, 3, 5, 7, 9, or 10 which is capable of storing two or more logical states.

12. A memory structure as in claims 1, 4, 6, 8, 2, 3, 5, 7, 9, or 10 wherein said first conductivity type is N and said second conductivity type is P.

13. A memory structure as in claim 12 wherein said second conductivity type is provided by boron dopants.

14. A structure as in claims 9, 10, 1, or 4 wherein said floating gate comprises a first layer of polycrystalline silicon, said first control gate comprises a second layer of polycrystalline silicon, and said second control gate comprises a third layer of polycrystalline silicon.

15. A structure as in claim 1, 4, 6, 8, 3, 3, 5, 7, or 9 wherein said source region and said drain region comprise buried diffusions.

2. A memory structure comprising:

a source region of a first conductivity type;

a drain region of said first conductivity type;

a first channel region of a second conductivity type opposite said first conductivity type, located adjacent said source region;

a second channel region of said second conductivity type, located between said drain region and said first channel region;

a floating gate located above said second channel region;

a first control gate formed by said drain and serving as a steering element for a memory transistor;

a second control gate located above said first channel region, serving as a control gate of an access transistor;

a tunneling zone formed between said floating gate and said second control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom, of said floating gate; and

a doped region at the interface of said first and second channel regions, said doped region being doped to said second conductivity type and having a greater dopant concentration than that of said first and second channel regions.

3. A memory structure comprising:

source region of a first conductivity type;

a drain region of said first conductivity type;

a first channel region of a second conductivity type opposite said first conductivity type, located adjacent said source region;

a second channel region of said second conductivity type, located between said drain region and said first channel region;

a floating gate located above said second channel region and having a tunneling portion separated from said second channel region by a tunneling dielectric;

a first control gate formed by said drain and serving as a steering element for a memory transistor; and

a second control gate located above said first channel region, serving as a control gate of an access transistor,

wherein said floating gate comprises a first layer of polycrystalline silicon, said first control gate comprises a buried diffusion layer, and said second control gate comprises a second layer of polycrystalline silicon.

4. A memory structure comprising:

a source region of a first conductivity type;

a drain region of said first conductivity type;

a first channel region of a second conductivity type opposite said first conductivity type, located adjacent said source region;

a second channel region of said second conductivity type, located between said drain region and said first channel region;

a floating gate located above said second channel region;

a first control gate located above said floating gate, serving as a steering element for a memory transistor;

a second control gate located above said first channel region, serving as a control gate of an access transistor;

a tunneling zone formed between said floating gate and said second control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said floating gate; and

a doped region at the interface of said first and second channel regions, said doped region being doped to said second conductivity type and having a greater dopan concentration than that of said first and second channel regions.

5. A memory structure comprising:

a source region of a first conductivity type;

a drain region of said first conductivity type;

a first channel region of a second conductivity type opposite said first conductivity type, located adjacent said source region;

a second channel region of said second conductivity type, located between said drain region and said first channel region;

a floating gate located above said second channel region and having a tunneling portion separated from said second channel region by a tunneling dielectric;

a first control gate formed by said drain and serving as a steering element for a memory transistor;

a second control gate located above said first channel region, serving as a control gate of an access transistor; and

a portion of said second channel region adjacent said drain region, said portion being doped to said second conductivity type to a dopant concentration greater than that of said second channel.

6. A memory structure comprising:

a source region of a first conductivity type;

a drain region of said first conductivity type;

a first channel region of a second conductivity type opposite said first conductivity type, located adjacent said source region;

a second channel region of said second conductivity type, located between said drain region and said first channel region;

a floating gate located above said second channel region;

a first control gate formed by said drain and serving as a steering element for a memory transistor;

a second control gate located above said first channel region, serving as a control gate of an access transistor; and

a tunneling zone formed between said floating gate and said second control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom, of said floating gate,

wherein said floating gate comprises a first layer of polycrystalline silicon, said first control gate comprises a buried diffusion, and second control gate comprises a second layer of polycrystalline silicon.

7. A memory structure comprising:

a source region of a first conductivity type;

a drain region of said first conductivity type;

a first channel region of a second conductivity type opposite said first conductivity type, located adjacent said source region;

a second channel region of said second conductivity type, located between said drain region and said first channel region;

a floating gate located above said second channel region and having a tunneling portion separated from said second channel region by a tunneling dielectric;

a first control gate formed by said drain and serving as a steering element for a memory transistor;

a second control gate located above said first channel region, serving as a control gate of an access transistor; and

a doped region at the interface of said first and second channel regions, said doped region being doped to said second conductivity type and having a greater dopant concentration than that of said first and second channel regions.

8. A memory structure comprising:

a source region of a first conductivity type;

a drain region of said first conductivity type;

a first channel region of a second conductivity type opposite said first conductivity type, located adjacent said source region;

a second channel region of said second conductivity type, located between said drain region and said first channel region;

a floating control gate located above said second channel region;

a first control gate formed by said drain and serving as a steering element for a memory transistor;

a second control gate located above said first channel region, serving as a control gate of an access transistor;

a tunneling zone formed between said floating gate and said second control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom, of said floating gate; and

a portion of said second channel region adjacent said drain region, said portion being doped to said second conductivity type to a dopant concentration greater than that of said second channel region.

9. A memory structure comprising:

a source region of a first conductivity type;

a drain region of said first conductivity type;

a first channel region of a second conductivity type opposite said first conductivity type, located adjacent said source region;

a second channel region of said second conductivity type, located between said drain region and said first channel region;

a floating gate comprising a first layer of polycrystalline silicon located above said second channel region;

a first control gate comprising a second layer of polycrystalline silicon located above said floating gate, serving as a steering element for a memory transistor;

a second control gate comprising a third layer of polycrystalline silicon located above said first channel region, serving as a control gate of an access transistor, said second control gate also overlying at least a portion of said first control gate; and

a tunneling zone formed between said floating gate and said second control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said floating gate.

10. A memory structure comprising:

a buried source region of a first conductivity type;

a buried drain region of said first conductivity type;

a first channel region of a second conductivity type opposite said first conductivity type, located adjacent said source region;

a second channel region of said second conductivity type, located between said drain region and said first channel region;

a floating gate located above said second channel region;

a first control gate located above said floating gate, serving as a steering element for a memory transistor;

a second control gate located above said first channel region, serving as a control gate of an access transistor;

a tunneling zone formed between said floating gate and said second control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said floating gate, and

a relatively thick dielectric layer overlying said buried diffusions.

16. A memory array having a plurality of memory cells, comprising:

a plurality of diffused lines running in a first direction, serving as source and drain regions of said memory cells, each memory cell having a first channel region located adjacent said source region and a second channel region located between said drain region and said first channel region;

a plurality of floating gates, each located above said second channel region of an associated one of said memory cells;

a plurality of first control gate lines, running in said first direction, located above an associated set of floating gates and serving as steering elements associated with each floating gate; and

a plurality of row lines, running in a second direction generally perpendicular to said first direction, forming a set of second control gates above said first channel regions of each memory cell, and serving as control gates of access transistors of associated memory cells,

wherein said memory cells are formed at the intersections of one of said diffused lines and one of said row lines, and

wherein each memory cell includes a tunnelling zone formed between said floating gate and said second control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said floating gate.

17. A memory array as in claim 16 wherein said source and drain regions are of N conductivity type and said channel regions are of P conductivity type.

18. A memory array as in claim 17 wherein said P conductivity type is provided by boron dopants.

19. A memory array as in claim 16 organized into a plurality of sectors, each sector comprising one or more columns of memory cells and organized such that erasure of all cells of a sector is performed simultaneously.

20. A memory array as in claim 19 organized as a virtual ground array.

21. A memory array as in claim 20 wherein said diffused lines comprise buried diffusions.

22. A memory array as in claim 19 wherein an entire column is written to simultaneously by placing data associated with each memory cell of the column on its associated row line, and causing all cells along said entire column to be written to.

23. A memory array as in claim 22 wherein all cells along an entire column are verified simultaneously by monitoring column current.

24. A memory array as in claim 19 organized into a plurality of sectors, each sector comprising one or more columns and organized such that writing of all cells in a column is performed simultaneously.

25. A memory array as in claim 24 wherein, bias voltages are removed from unselected columns in order to minimize disturb to the charge stored on said floating gates of said unselected columns during reading and/or writing.

26. An array as in claim 19 wherein each memory cell is capable of storing two or more logical states.

27. A memory array as in claim 16 organized into a plurality of sectors, each sector comprising one or more rows and organized such that erasure of all cells of a sector is performed simultaneously.

28. A memory array as in claim 27 wherein alternate bits in a given row are verified simultaneously.

29. A memory array as in claim 28 wherein an entire row is verified utilizing two verification operations.

30. A memory array as in claim 27 wherein alternate bits in a given row are programmed simultaneously by placing data associated with each memory cell to be programmed on its associated column line.

31. A memory array as in claim 30 wherein an entire row is programmed utilizing two program operations.

32. A memory array having a plurality of memory cells, comprising:

a plurality of metal bit lines running in a first direction, each said bit line having contact means for electrically contacting diffused regions, said diffused regions serving as source regions of said memory cells;

a plurality of diffused lines running in a second direction generally perpendicular to said first direction, serving as drain regions of said memory cells, each memory cell having a first channel region located adjacent an associated one of said source regions and a second channel region located between an associated one of said drain regions and said first channel region;

a plurality of floating gates, each located above said second channel region of an associated one of said memory cells;

a plurality of first control gate lines, running in said second direction, located above an associated set of floating gates and serving as steering elements associated with said floating gates; and

a plurality of row lines, running in said second direction, forming a set of second control gates above said first channel regions of each memory cell, and serving as a control gate of an access transistor of each memory cell,

wherein said memory cells are formed at the intersections of one of said diffused lines and one of said row lines, and

wherein each memory cell includes a tunnelling zone formed between said floating gate and said second control gate, and including one or more of edges, side wall, corners of the top edge, portions of the top, and portions of the bottom of said floating gate.

33. A memory array as in claim 32 organized into a plurality of sectors, each sector comprising one or more rows and organized such that erasure of all cells of a sector is performed simultaneously.

34. An array as in claim 33 wherein each memory cell is capable of storing two or more logical states.

35. A memory array as in claim 33 wherein an entire row is written to simultaneously by placing data associated with each memory cell of the column on its associated column line, and causing all cells along said selected row to be written to.

36. A memory array as in claim 33 wherein all cells along an entire row are verified simultaneously.

37. A memory array as in claim 32 organized into a plurality of sectors, each sector comprising one or more rows and organized such that writing of all cells of a row is performed simultaneously.

38. A memory array as in claim 32 organized into a plurality of sectors, each sector comprising one or more rows and organized such that verification of all cells of a row is performed simultaneously.

39. An array as in claim 32 wherein each memory cell is capable of storing two or more logical states.

40. An array as in claim 32 which further comprises ground contact means coupled to each drain region, wherein said memory array is organized into a plurality of sectors, each sector comprising one or more rows, such that one or more of said ground contact means is associated with each said sector.

41. A memory structure as in claim 32 wherein said source and drain regions are of N conductivity type and said channel regions are of P conductivity type.

42. A memory structure as in claim 41 wherein said P conductivity type is provided by boron dopants.