Method and apparatus for deskewing digital data

• US 5,313,501 A
• Filed: 06/15/1992
• Issued: 05/17/1994
• Est. Priority Date: 06/15/1992
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Thacker, Charles P.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Bocure, Tesfaldet
• Application Number:
  US07/898,335
• Time in Patent Office: 701 Days
• Field of Search: 375/117, 375/118, 375/107, 375/106, 307/262, 307/269, 307/602, 307/590, 328/55, 328/755, 371/1
• US Class Current: 375/369
• CPC Class Codes: H04L 25/45 using electronic distributors
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop
• CPC Class Codes: H04L 7/044 using a single bit, e.g. start stop bit

Abstract

In a computer system, parallel streams of digital data are transmitted from a source to a destination in bursts or packets. At the beginning of each burst all the parallel data signals contain a start bit. Each data signal is received by a deskewing buffer which transmits the data signal through a delay line with multiple taps. At the beginning of each clock cycle the signal value Data(i) at each tap (i) in the delay line is latched. Each resulting latched signal value LData(i) is compared with the latched signal value LData(i+1) for the next tap down the delay line to generate a set of comparison signals C(i). When the start bit of a new burst is received, one of the comparison signals will have a distinct value from all the others, thereby indicating the delay line tap at which the phase of the received data signal is approximately synchronized with the receiver'"'"'s clock signal. The data stored in the deskewing buffer'"'"'s latches represents the phase of the received digital signal and is retained until the end of the burst transmission. A multiplexer which outputs a selected one of data signals from the tapped delay line in accordance with the values of the comparison signals. The selected data signal is sampled and latched at each clock cycle, thereby generating a deskewed data signal that is synchronized with both the receiver'"'"'s clock signal and also with the other parallel data streams.

Claims

1. A receiver circuit for deskewing N parallel digital data signals that are transmitted in bursts, each burst beginning with a predefined start bit in each said parallel digital data signal, the receiver circuit comprising:

a receiver clock circuit for generating a read clock signal;

N data ports for receiving said N parallel digital data signals, where N is a positive integer greater than one;

N tapped delay lines, each tapped delay line comprising a chain of delay elements through which said received digital data signal is transmitted, said chain of delay elements generating delayed digital signals at signal taps located after each of said delay elements;

comparison means for comparing each said delayed digital signal from each said tapped delay line with an immediately neighboring delayed digital signal from the same tapped delay line so as to detect a signal transition indicative of said start bit;

latch means, coupled to said receiver clock circuit and said tapped delay lines, for storing data corresponding to the signal tap at which said signal transition was located in each said tapped delay line at a predefined time during a cycle of said read clock signal;

a multiplexer, coupled to said comparison means and said tapped delay lines, that outputs one of said delayed digital signals from each of said tapped delay lines in accordance with said data stored by said latch means; and

logic means for storing new data in said latch means as each new burst of digital data signals is received;

whereby said data signals output by the multiplexers are synchronized with said read clock signal and with each other.

2. A receiver circuit for deskewing N parallel digital data signals that are transmitted in bursts, each burst beginning with a predefined start bit in each said parallel digital data signal, the receiver circuit comprising:

a receiver clock circuit for generating a latch clock signal and a read clock signal that is synchronized with said latch clock signal;

N deskewing buffers, each buffer receiving a distinct one of said N parallel digital data signals, where N is a positive integer greater than one;

each deskewing buffer comprising;

a data port for receiving one of said digital data signals;

a chain of J delay elements through which said digital data signal received by said data port is transmitted, said chain of J delay elements generating J delayed digital signals Data(i), for i=1 to J, at signal taps located after each of said delay elements;

a latch that latches said J delayed digital signals Data(i) at a predefined time during each cycle of said latch clock signal, thereby generating J latched digital signals LData(i);

a logic circuit coupled to said latch for comparing said latched digital signals LData(i) with the latched digital signals LData(i+1) for i=1 to J-1, generating J-1 comparison signals C(i);

wherein when said predefined start bit is received and latched into said latch, one of comparison signals will have a predefined value distinct from all the other ones of said comparison signals; and

a multiplexer which receives said data signals Data(i) and outputs one of said data signals Data(i) in accordance with the one of said comparison signals having said predefined value; and

a latch clock inhibiting circuit for inhibiting generation of said latch clock signal after said predefined start bit has been received by all of said deskewing buffers;

whereby said data signals output by the multiplexers in said deskewing buffers are synchronized with said read clock signal and with each other.

3. A method of deskewing N parallel digital data signals that are transmitted in bursts, each burst beginning with a predefined start bit in each said parallel digital data signal, the steps of the method comprising:

generating a read clock signal;

receiving said N parallel digital data signals, where N is a positive integer greater than one;

transmitting each of said received N parallel digital data signals through a separate tapped delay line, each said chain of delay elements generating delayed digital signals at signal taps located after each of said delay elements;

comparing each said delayed digital signal from each said tapped delay line with an immediately neighboring delayed digital signal from the same tapped delay line so as to detect a signal transition indicative of said start bit;

storing, in a latch, data corresponding to the signal tap at which said signal transition was located in each said tapped delay line at a predefined time during a cycle of said read clock signal;

outputting one of said delayed digital signals from each of said tapped delay lines in accordance with said stored data; and

storing new data in said latch as each new burst of digital data signals is received;

whereby said data signals output by said outputting step are synchronized with said read clock signal and with each other.

4. A method of deskewing N parallel digital data signals that are transmitted in bursts, each burst beginning with a predefined start bit in each said parallel digital data signal, the steps of the method comprising:

generating a latch clock signal and a read clock signal that is synchronized with said latch clock signal;

receiving said N parallel digital data signals, where N is a positive integer greater than one;

processing each received digital data signal by;

transmitting said received digital data signal through a chain of J delay elements, said chain of J delay elements generating J delayed digital signals Data(i), for i=1 to J, at signal taps located after each of said delay elements;

latching said J delayed digital signals Data(i) at a predefined time during each cycle of said latch clock signal, thereby generating J latched digital signals LData(i);

comparing said latched digital signals LData(i) with the latched digital signals LData(i+1) for i=1 to J-1, generating J-1 comparison signals C(i);

wherein when said predefined start bit is received and latched, one of said comparison signals will have a predefined value distinct from all the other ones of said comparison signals; and

outputting one of said data signals Data(i) in accordance with the one of said comparison signals having said predefined value; and

inhibiting generation of said latch clock signal after said predefined start bit has been received by all of said deskewing buffers;

whereby said data signals output by said outputting step are synchronized with said read clock signal and with each other.