Method and device for protecting data of ROM

• US 5,313,520 A
• Filed: 01/29/1993
• Issued: 05/17/1994
• Est. Priority Date: 03/09/1990
• Status: Expired due to Term

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Gold Star Electron Company Limited
• Inventors: Han, Dae K.
• Primary Examiner(s): Gregory, Bernarr E.
• Application Number:
  US08/011,105
• Time in Patent Office: 473 Days
• Field of Search: 380/3, 380/4, 380/23, 380/25, 380/50, 380/49, 340/825.31, 340/825.34
• US Class Current: 711/163
• CPC Class Codes: G06F 12/1466 Key-lock mechanism

Abstract

A method and a device are provided for protecting data stored in a ROM of a micoprogram control unit. Such data may take the form of a user program. To protect the data, predetermined code data is written into a predetermined address in the ROM. A code address inputted from outside the microprogram control unit is then compared with the predetermined address. If the inputted code address is determined to match the predetermined address, then code data inputted from outside the microprogram control unit is compared with the predetermined code data. Only after both of these comparisons are successfully made is the data in the ROM allowed to be read outside the microprogram control unit.

Claims

1. A method for protecting data stored in a ROM of a microprogram control unit comprising the steps of:

writing predetermined code data into a specific address of the ROM;

checking whether a code address inputted from outside the microprogram control unit agrees with the specific address where the predetermined code data was stored;

checking whether code data inputted from outside the microprogram control unit agrees with the predetermined code data after the inputted code address is determined to agree with the specific address where the predetermined code data was stored;

changing a status bit from a first state to a second state after the inputted code data is determined to agree with the predetermined code data;

denying access to the data stored in the ROM when the status bit is set to the first state; and

allowing data stored in the ROM to be read outside of the microprogram control unit only when the status bit is set to the second state.

2. A device for protecting data stored in a ROM of a microprogram control unit comprising:

a) a code address comparison circuit which, after receiving a mode control signal from outside of the microprogram control unit indicating an attempt to read the data stored in the ROM,

i) checks whether a code address inputted from outside the microprogram control unit agrees with a predetermined code address previously stored in the code address comparison circuit, and then

ii) outputs an address matching signal and the stored predetermined code address when the inputted code address agrees with the stored predetermined code address;

b) a ROM which outputs predetermined code data stored at the predetermined code address after the ROM receives the predetermined code address outputted from the code address comparison control circuit;

c) a comparison circuit which

i) compares the predetermined code data outputted from the ROM with code data inputted from outside the microprogram control unit, and when the predetermined code data and the inputted code data agree with each other,

ii) outputs a code data matching signal to cause a status bit, which is outputted outside the microprogram control unit and which has two states, to change from one state to the other state and, at the same time,

iii) checks the state of the status bit and, when the status bit is set to a predetermined state, then

iv) outputs an address reset signal to enable data stored in the ROM to be read to outside the microprogram control unit; and

d) a program counter which

i) deactivates when the program counter receives the mode control signal, and which

ii) activates and resets an internal address counter to zero when the program counter receives the address reset signal.

3. A device according to claim 2 for protecting data stored in a ROM of a microprogram control unit, further comprising:

e) a code input control circuit which allows code data inputted from outside the microprogram control unit to reach the comparison circuit only after the code input control circuit receives the address matching signal.

4. A device according to claim 2 for protecting data stored in a ROM of a microprogram control unit, further comprising:

e) a ROM data output control circuit which allows data from the ROM to be outputted to outside the microprogram control unit only after the ROM data output control circuit receives the address reset signal.

5. A device according to claim 2 for protecting data stored in a ROM of a microprogram control unit, further comprising:

e) a status output control circuit which outputs the value of the status bit to outside the microprogram control unit after the status output control circuit receives the code data matching signal.

6. A device for protecting data stored in a ROM of a microprogram control unit by preventing the data from being read outside of the device until after an appropriate inputted address and an appropriate inputted code are received by the device, the device comprising:

the ROM containing the data and having predetermined code data at a predetermined address;

an input-output bus;

an address comparison circuit connected to the input-output bus for comparing with the predetermined address the inputted address which is inputted on the input-output bus;

an address bus connected between the address comparison circuit and the ROM which carries the predetermined address from the address comparison circuit to the ROM when the inputted address matches the predetermined address;

a data bus connected to the ROM which carries the data from the ROM when an address associated with the data is received by the ROM on the address bus; and

a code data comparison circuit, connected to the data bus and the input-output bus, which receives the predetermined code data on the data bus after the ROM receives the predetermined address on the address bus, and which compares the predetermined code data with the inputted code data which is inputted on the input-output bus;

a data access controlling means for controlling access to the ROM by

a) preventing the ROM from receiving addresses directly from the input-output bus, so that the ROM is incapable of outputting ROM data, before the address comparison means determines that the predetermined address matches the inputted address and the code data comparison means determines that the predetermined code data matches the inputted code data, and

b) allowing the ROM to receive addresses directly from the input-output bus and output ROM data after the address comparison means determines that the predetermined address matches the inputted address and the code data comparison means determines that the predetermined code data matches the inputted code data.

7. The device of claim 6 further comprising:

a status output control circuit connected to the input-output bus and having a status bit with two states; and

a code data matching signalling means for carrying a code data matching signal from the code data comparison circuit to the status output control circuit when the predetermined code data matches the inputted code data, the status output control circuit outputting a status signal on the input-output bus and changing the state of the status bit when the status output control circuit receives the code data matching signal.

8. The device of claim 7 further comprising:

a code input control circuit connected between the code data comparison circuit and the input-output bus; and

an address matching signalling means for carrying an address matching signal from the address comparison circuit to the code input control circuit when the inputted address matches the predetermined address, the code input control circuit allowing code data to travel from the input-output bus to the code data comparison circuit only after the code input control circuit receives the address matching signal.

9. The device of claim 8 further comprising:

a status bit signalling means connected from the status output control circuit to the code data comparison circuit for indicating the current state of the status bit of the status output control circuit;

a ROM data output control circuit connected between the data bus and the input-output bus; and

an output signalling means for carrying an output signal from the code data comparison circuit to the address comparison circuit and the ROM data output control circuit when the status bit signalling means indicates to the code data comparison circuit that the status bit of the status output control circuit has ben changed, the address comparison circuit and the ROM data output control circuit allowing the ROM data to be outputted to the input-output bus only after the output signal is received.

10. The device of claim 9 further comprising:

a mode control input pin adapted for receiving an input signal having a first and second state; and

a mode control signalling means for carrying a mode control signal from the mode control input pin to the address comparison circuit to indicate when the input signal on the mode control input pin is converted from the first state to the second state,

the address comparison circuit comparing the address inputted on the input-output bus with the predetermined address only after the address comparison circuit receives the mode control signal.