Multiport memory bypass under software control

• US 5,313,551 A
• Filed: 02/11/1991
• Issued: 05/17/1994
• Est. Priority Date: 12/28/1988
• Status: Expired due to Fees

• Current Assignee: Foothills IP LLC
• Original Assignee: North American Philips Corp. (Koninklijke Philips N.V.)
• Inventors: Slavenburg, Gerrit A., Labrousse, Jean-Michel J.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Vu, Viet
• Application Number:
  US07/654,847
• Time in Patent Office: 1,191 Days
• Field of Search: 395/500, 395/800, 395/375, 395/400, 395/425
• US Class Current: 711/149
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute

Abstract

A program-controlled processing device includes a multiport memory circuit providing a plurality of storage locations. First and second data ports of the memory circuit provide parallel access to different locations in accordance with first and second addresses encoded in the program instructions. Bypass means is provided for coupling the second data port to the first data port to simulate parallel access to the same location when desired. The bypass means is controlled directly by the program instructions, by means of a separate bypass control field or by a special value of one of the two addresses. There is thus no need for a run-time comparison of addresses before each memory access, leading to a faster operation of the memory circuit.

Claims

1. A data processing device structured for operation under control of a sequence of instructions forming a program, the device including:

(a) storage means including a plurality of storage locations each having their own address and having at least first and second data ports for providing parallel access to storage locations at different addresses in accordance with respective first and second addresses encoded in a first type of program instruction,

(b) said sequence of instructions including a second type of program instruction which includes an explicitly encoded bypass signal to simulate parallel access of both data ports to a storage location at the same address,

(c) bypass means responsive to said bypass signal upon execution of said second type of program instruction for connecting the second data port to the first data port to avoid simultaneous parallel access by both data ports to the storage location at the same address.

2. A processing device as claimed in claim 1 wherein the first data port is a write port of the storage means and the second data port is a read port of the storage means.

3. A processing device as claimed in claim 1 wherein the bypass signal is encoded separately from the first and second addresses, in a bypass control field contained in each program instruction of the first or second type.

4. A processing device as claimed in claim 1 wherein in the second type of program instruction the bypass signal is encoded as a special value in a field which in an instruction of the first type contains one of the first and second addresses.

5. A processing device as claimed in claim 2 wherein the bypass signal is encoded separately from the first and second addresses, in a bypass control field contained in each program instruction of the first or second type.

6. A processing device as claimed in claim 2 wherein in the second type of program instruction the bypass signal is encoded as a special value in a field which in an instruction of the first type contains one of the first and second addresses.

7. A processing device as claimed in claim 6 wherein the bypass signal is encoded as a special value of a field which in an instruction of the first type contains the second address.

8. A processing device as claimed in claim 2 further including:

a processing element having a data input and a data output and being constructed to operate synchronously with the storage means under control of the instructions,

wherein the storage means forms a register file for buffering intermediate results between the data output and the data input of the processing element.

9. A processing device as claimed in claim 8 wherein the processing element is one of a plurality of processing elements constructed to operate synchronously with one another under control of respective fields of the program instructions, and wherein the storage means forms at least part of a multiport register file interconnecting respective data inputs and data outputs of at least two of the processing elements.

10. A processing device as claimed in claim 8 wherein the bypass signal is encoded separately from the first and second addresses, in a bypass control field contained in each program instruction of the first or second type.

11. A processing device as claimed in claim 8 wherein the second type of program instruction the bypass signal is encoded as a special value in a field which in an instruction of the first type contains one of the first and second addresses.

12. A processing device as claimed in claim 11 wherein the bypass signal is encoded as a special value of a field which in an instruction of the first type contains the second address.

13. A method of operating a processing device constructed in accordance with claim 1, the method comprising:

defining a desired sequence of operations for the device, including parallel first and second sequences of accesses to locations in the storage means via the first and second data ports respectively;

identifying in the first and second access sequences desired parallel accesses to the same location; and

generating a sequence of instructions for controlling the operation of the device to effect the first and second access sequences, the generated sequence including instructions of the second type to effect the identified parallel accesses.

14. A method of operating a processing device constructed in accordance with claim 8, the method comprising:

defining a desired sequence of operations for the device, including parallel first and second sequences of accesses to locations in the storage means via the first and second data ports respectively;

identifying in the first and second access sequences desired parallel accesses to the same location; and

generating a sequence of instructions for controlling the operation of the device to effect the first and second access sequences, the generated sequence including instructions of the second type to effect the identified parallel accesses.

15. A method of operating a processing device constructed in accordance with claim 11, the method comprising:

defining a desired sequence of operations for the device, including parallel first and second sequences of accesses to locations in the storage means via the first and second data ports respectively;

identifying in the first and second access sequences desired parallel accesses to the same location; and

generating a sequence of instructions for controlling the operation of the device to effect the first and second access sequences, the generated sequence including instructions of the second type to effect the identified parallel accesses.

16. A method of operating a processing device constructed in accordance with claim 12, the method comprising:

defining a desired sequence of operations for the device, including parallel first and second sequences of accesses to locations in the storage means via the first and second data ports respectively;

identifying in the first and second access sequences desired parallel accesses to the same location; and

generating a sequence of instructions for controlling the operation of the device to effect the first and second access sequences, the generated sequence including instructions of the second type to effect the identified parallel accesses.

17. A multiport memory circuit comprising:

(a) an array of data storage locations associated with respective different address values,

(b) first and second data ports for writing data to and reading data from said first and second data ports,

(c) address decoding means for receiving respective first and second address values and for enabling parallel access via the first and second data ports to respective data storage locations in accordance with received address values,

(d) bypass means for connected the second data port to the first data port to avoid accessing any data storage locations in response to the decoding means receiving a predetermined value of at least one of the received addresses, said predetermined value being different from the address values associated with any of the data storage locations in the array and not being capable of addressing any of such data storage locations, so as to simulate parallel access of both data ports to a storage location at the same address.

18. A memory circuit as claimed in claim 17 wherein the first data port is a write port of the storage means and the second data port is a read port of the storage means.

19. A memory circuit as claimed in claim 18 wherein the bypass means is responsive to a special value of the second address.