System for controlling communications among a computer processing unit and a plurality of peripheral devices

• US 5,313,597 A
• Filed: 07/27/1993
• Issued: 05/17/1994
• Est. Priority Date: 08/31/1990
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Gephardt, Douglas D.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Toplu, Lucien
• Application Number:
  US08/097,868
• Time in Patent Office: 294 Days
• Field of Search: 364/DIG. 1, 364/DIG. 2
• US Class Current: 710/316
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

A system for controlling communications among a computer processing unit and a plurality of peripheral devices which are arrayed in operative connection with a plurality of external buses. The system comprises a bus control circuit for effecting operative routing of address information regarding a respective peripheral device from the computer processing unit to an appropriate external bus, the respective peripheral device being in operative connection with the appropriate external bus. The bus control circuit also effects operative routing of data information from the respective peripheral device to another of the plurality of peripheral devices or to the computer processing unit according to the address information. The system further comprises a plurality of buffers for establishing operative interfaces between the system and each of the plurality of external buses and an internal bus for facilitating communications among the plurality of buffers, the bus control circuit, and the computer processing unit. The bus control circuit enables operative interconnections to the internal bus by the plurality of buffers and the computer processing unit and includes an information storage unit for retaining stored routing information representing all operative interconnections which can operatively occur, the bus control circuit effecting such enabling according to the stored routing information.

Claims

1. A system for providing communications among a computer processing unit and a plurality of peripheral devices, said plurality of peripheral devices being arrayed in operative connection with a plurality of external buses;

each respective peripheral device of said plurality of peripheral devices being uniquely identified by an address contained in address information;

the system comprising;

a bus control means operatively connected with said computer processing unit and cooperating with said computer processing unit for effecting operative routing of selected address information of said address information identified by said computer processing unit regarding a particular said address identifying a particular peripheral device of said plurality of peripheral devices from said computer processing unit to an appropriate external bus of said plurality of external buses, said particular peripheral device being in said operative connection with said appropriate external bus, said bus control means routing data information intermediate said particular peripheral device and another of said plurality of peripheral devices or said computer processing unit via an internal bus in response to said selected address information identified by said computer processing unit; and

a plurality of buffer means for establishing an operative interface between said computer processing unit and each of said plurality of external buses, said plurality of buffer means cooperating to substantially capacitively isolate each respective external bus of said plurality of external buses from other external buses of said plurality of external buses than said respective external bus;

said internal bus being operatively connected to provide communication paths among said plurality of buffer means, said bus control means, and said computer processing unit;

said bus control means including an information storage means for retaining stored routing information, said stored routing information representing each correspondence between each said particular peripheral deice and a particular buffer means of said plurality of buffer means, said bus control means effecting said routing of data information using selected routing information, said selected routing information being selected from said stored routing information in response to said selected address information.

2. A system for providing communications among a computer processing unit and a plurality of peripheral devices as recited in claim 1 wherein said bus control means, said internal bus, said computer processing unit, and said plurality of buffer means are configured as an integrated circuit on a single substrate and wherein the system further comprises a plurality of additional on-board peripheral devices, said plurality of on-board peripheral devices being integrated within the system and operatively connected with said internal bus means, each of said plurality of additional on-board peripheral devices having an address and being accessed for communications.

3. A system for providing communications between a computing apparatus and a plurality of peripheral devices located externally of said computing apparatus, said plurality of peripheral devices being arrayed in operative connection with a plurality of external buses;

said computer apparatus including a computer processing unit;

said computer processing unit and each respective peripheral device of said plurality of peripheral devices being uniquely identified by an address;

the system comprising;

a plurality of buffer means for establishing an interface between said computing apparatus and said plurality of external buses, there at least being one respective buffer means of said plurality of buffer means for each respective external bus of said plurality of external buses, said plurality of buffer means cooperating to substantially capacitively isolate each respective external bus of said plurality of external buses from other external buses of said plurality of external buses than said respective external bus;

an internal bus means for providing communication path routing within the system, said internal bus means operatively connecting said plurality of buffer means with said computer processing unit; and

a bus control means for controlling routing of data among said computer processing unit and said plurality of peripheral devices;

said bus control means being operatively connected with said internal bus means and said computer processing unit;

said bus control means including an information storage means for retaining stored routing information representing selected correspondence between each said respective peripheral device with said at least one respective buffer means, said bus control means responding to signals received from said computer processing unit to select specified routing information from said stored routing information for establishing communication path routing required by said signals.

4. A system for providing communications among a computer processing unit and a plurality of peripheral devices, said plurality of peripheral devices being arrayed in operative connection with a plurality of external buses;

each respective peripheral device of said plurality of peripheral devices being uniquely identified by an address contained in address information;

the system comprising;

a bus control means operatively connected with said computer processing unit and cooperating with said computer processing unit for effecting operative routing of selected address information of said address information identified by said computer processing unit regarding a particular said address identifying a particular peripheral device of said plurality of peripheral devices from said computer processing unit to an appropriate external bus of said plurality of external buses, said particular peripheral device being in said operative connection with said appropriate external bus, said bus control means routing data information intermediate said particular peripheral device and another of said plurality of peripheral devices or said computer processing unit via an internal bus in response to said selected address information identified by said computer processing unit; and

a plurality of buffer means for establishing an operative interface between said computer processing unit and each of said plurality of external buses;

said internal bus being operatively connected to provide communication paths among said plurality of buffer means, said bus control means, and said computer processing unit;

said bus control means including an information storage means for retaining stored routing information, said stored routing information representing each correspondence between each said particular peripheral device and a particular buffer means of said plurality of buffer means, said bus control means effecting said routing of data information using selected routing information, said selected routing information being selected from said stored routing information i response to said selected address information.

5. A system for controlling communications among a computer processing unit and a plurality of peripheral devices as recited in claim 4 wherein the system further comprises a plurality of on-board peripheral devices, said plurality of on-board peripheral devices being integrated within the system and operatively connected with said internal bus means, each of said plurality of on-board peripheral devices having an address.

6. A system for providing communications between a computing apparatus and a plurality of peripheral devices located externally of said computing apparatus, said plurality of peripheral devices being arrayed in operative connection with a plurality of external buses;

said computing apparatus including a computer processing unit;

said computer processing unit and each respective peripheral device of said plurality of peripheral devices being uniquely identified by an address;

the system comprising;

a plurality of buffer means for establishing an interface between said computing apparatus and said plurality of external buses, there at least being one respective buffer means of said plurality of buffer means for each respective external bus of said plurality of external buses;

an internal bus means for providing communication path routing within the system, said internal bus means operatively connecting said plurality of buffer means with said computer processing unit; and

a bus control means for controlling routing of data among said computer processing unit and said plurality of peripheral devices;

said bus control means being operatively connected with said internal bus means and said computer processing unit;

said bus control means including an information storage means for retaining stored routing information representing selected correspondences between each said respective peripheral device with said at least one respective buffer means, said bus control means responding to signals received from said computer processing unit to select specified routing information from said stored routing information for establishing communication path routing required by said signals.