Optimum write-back strategy for directory-based cache coherence protocols
First Claim
1. A system for optimizing the performance of a multiprocessor system having write-back caches and a multistage interconnection network connected to a shared memory, by allowing concurrent line transfer and write-back operations, comprising:
- a modified word buffer configured to store any modified words within a modified cache line when said modified words are written back from a cache;
a line buffer configured to store an old cache line transferred from said memory, said old cache line corresponding in address identity with said modified cache line; and
a global directory associated with said modified word buffer and said line buffer, said global directory configured to store state and control information pertaining to cache lines, said global directory configured to request a write-back of said modified words from said cache and concurrently request said old cache line from said memory, and said global directory configured to cause said modified word buffer and said line buffer to write, in combination, said modified cache line to a requesting cache.
1 Assignment
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Accused Products
Abstract
A directory-based protocol is provided for maintaining data coherency in a multiprocessing (MP) system having a number of processors with associated write-back caches, a multistage interconnection network (MIN) leading to a shared memory, and a global directory associated with the main memory to keep track of state and control information of cache lines. Upon a request by a requesting cache for a cache line which has been exclusively modified by a source cache, two buffers are situated in the global directory to collectively intercept modified data words of the modified cache line during the write-back to memory. A modified word buffer is used to capture modified words within the modified cache line. Moreover, a line buffer stores an old cache line transferred from the memory, during the write back operation. Finally, the line buffer and the modified word buffer, together, provide the entire modified line to a requesting cache.
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Citations
17 Claims
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1. A system for optimizing the performance of a multiprocessor system having write-back caches and a multistage interconnection network connected to a shared memory, by allowing concurrent line transfer and write-back operations, comprising:
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a modified word buffer configured to store any modified words within a modified cache line when said modified words are written back from a cache; a line buffer configured to store an old cache line transferred from said memory, said old cache line corresponding in address identity with said modified cache line; and a global directory associated with said modified word buffer and said line buffer, said global directory configured to store state and control information pertaining to cache lines, said global directory configured to request a write-back of said modified words from said cache and concurrently request said old cache line from said memory, and said global directory configured to cause said modified word buffer and said line buffer to write, in combination, said modified cache line to a requesting cache. - View Dependent Claims (2, 3)
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4. A system for optimizing the performance of a multiprocessor system having write-back caches and a multistage interconnection network connected to a shared memory by allowing concurrent line transfer and write-back operations, comprising:
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control means for receiving requests for a modified cache line from a requesting cache, for requesting a write-back of modified words in said modified cache line from a source cache and concurrently requesting a transfer of an old cache line from the memory, said old cache line corresponding in address identity with said modified cache line, and for transferring said modified cache line to said requesting cache; and buffer means, connected to said control means, for capturing said modified words written back from said source cache and concurrently storing said old cache line from the memory. - View Dependent Claims (5, 6, 7)
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8. A method for controlling the performance of a multiprocessor system having write-back caches and a multistage interconnection network connected to a shared memory monitored by a global directory, the method for allowing concurrent line transfer and write-back operations, comprising the steps of:
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(a) requesting the global directory for a modified cache line; (b) requesting a write-back of modified words in said modified cache line from a source cache and concurrently requesting a transfer of an old cache line from the memory, said old cache line corresponding in address identity with said modified cache line; (c) capturing in said global directory said modified words written back from said source cache and concurrently storing in said global directory said old cache line from said memory; and (d) transferring from said global directory said modified cache line. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification