Fault recoverable computer system

• US 5,313,625 A
• Filed: 07/30/1991
• Issued: 05/17/1994
• Est. Priority Date: 07/30/1991
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Yount, Larry J., Hess, Richard F.
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US07/738,011
• Time in Patent Office: 1,022 Days
• Field of Search: 371/12, 371/68.3, 395/575
• US Class Current: 714/10
• CPC Class Codes: G06F 11/1402 Saving, restoring, recovering or retrying
• CPC Class Codes: G06F 11/1407 Checkpointing the instruction stream
• CPC Class Codes: G06F 11/1633 using mutual exchange of the output between the redundant processing components
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring

Abstract

In a computer system having fault recoverable capability, there is included a first and second data processing unit (DPU), wherein each of the first and second DPU is executing the same task essentially in parallel. Each DPU comprises a processor, a memory and a protected memory. The protected memory stores system data, such that the system data stored in the protected memory is immune from transient conditions. Also included is a monitor, which is operatively connected to the monitor of the other DPU. The monitor detects the occurrence of an upset to reinitialize the DPU, the DPU being reinitialized to a condition just prior to the occurrence of the upset thus avoiding utilization of any potentially erroneous data, and thereby permitting the DPU to return to its normal processing with valid data.

Claims

1. In a computer system having fault recoverable capability, and including a first and second data processing unit (DPU), wherein each of said first and second DPU is executing the same task essentially in parallel, each DPU comprising:

a) processing means;

b) memory means, operatively connected to said processing means, for storing information;

c) protected memory means, operatively connected to said memory means and to said processing means, for storing system data, wherein said system data stored in said protected memory means is immune from transient conditions; and

d) monitor means, operatively connected to said processing means, said memory means, and said protected memory means of the associated DPU, and further wherein the monitor means of the first DPU is operatively connected to said second DPU and wherein the monitor means of the second DPU is operatively connected to the first DPU, for detecting the occurrence of an upset within the computer system to reinitialize the corresponding DPU, the DPU being reinitialized by said system data from the protected memory means of the corresponding DPU to a condition just prior to the occurrence of the upset thus avoiding utilization of any potentially erroneous data, and thereby permitting the DPU to return to its normal processing with valid data.

2. In a computer system having fault recoverable capability according to claim 1, wherein said monitor means comprises:

a) in-line monitor means, operatively connected to the corresponding DPU, for verifying data processing of the corresponding DPU is proceeding normally; and

b) cross-lane monitor means, operatively connected to the corresponding DPU and to the cross-lane monitoring means of the other DPU, for comparing predetermined data generated by the DPU with the predetermined data generated by the other DPU.

3. In a computer system having fault recoverable capability according to claim 2, wherein said protected memory means comprises:

a) first memory means, for storing recovery information associated with a present computational frame;

b) second memory means, for storing recovery information associated with at least one previous computational frame; and

c) memory control means, for controlling the storage of recovery information in said first memory means and said second memory means upon error-free completion of the currently executing computational frame in response to a write control signal from said monitor means.

4. In a computer system having fault recoverable capability according to claim 3, wherein said cross-lane monitor means comprises:

a) first monitor means for verifying errorless DPU system performance; and

b) second monitor means for comparing computer data between the DPUs, said monitor means generating an error signal if predetermined criteria of the verifying or comparing function have not been met.

5. In a computer system having fault recoverable capability according to claim 4, wherein said monitor means further comprises:

logic means, operatively connected to data processing means, memory means, and protected memory means, for reinitializing said DPU in response to a recovery control signal.

6. In a computer system having fault recoverable capability according to claim 2, wherein said monitor means further comprises:

logic means, operatively connected to said processing means, memory means, and protected memory means, for reinitializing said DPU in response to a recovery control signal.

7. In a computer system having fault recoverable capability according to claim 5, wherein said monitor means includes at least one specific processing means, said specific processing means being less complex than said processing means.

8. In a computer system having fault recoverable capability, and including at least a first and second data processing unit (DPU), wherein each of said first and second DPU is executing the same task essentially in parallel, each DPU comprising:

a) processing means;

b) memory means, operatively connected to said processing means, for storing information;

c) protected memory means, operatively connected to said memory means and to said processing means, for storing system data, wherein said system data stored in said protected memory means is immune from transient conditions; and

d) monitor means, operatively connected to said processing means, said memory means, and said protected memory means of the associated DPU, and further operatively connected to each of said other DPUs, for detecting the occurrence of an upset within the computer system to reinitialize the corresponding DPU, the DPU being reinitialized by said system data from the protected memory means of the corresponding DPU to a condition just prior to the occurrence of the upset thus avoiding utilization of any potentially erroneous data, and thereby permitting the DPU to return to its normal processing with valid data.

9. In a computer system having fault recoverable capability according to claim 8, wherein said monitor means comprises:

a) in-line monitor means, operatively connected to the DPU, for verifying data processing of the corresponding DPU is proceeding normally; and

b) cross-lane monitor means, operatively connected to the corresponding DPU and to each of the cross-lane monitoring means of the other DPUs, for comparing predetermined data generated by the DPU with the predetermined data generated by the other DPUs.

10. In a computer system having fault recoverable capability according to claim 9, wherein said protected memory means comprises:

a) first memory means, for storing recovery information associated with a present computational frame;

b) second memory means, for storing recovery information associated with at least one previous computational frame; and

c) memory control means, for controlling the storage of recovery information in said first memory means and said second memory means upon error-free completion of the currently executing computational frame in response to a write control signal from said monitor means.

11. In a computer system having fault recoverable capability according to claim 10, wherein said cross-lane monitor means comprises:

a) first monitor means for verifying errorless DPU system performance; and

b) second monitor means for comparing computer data between the DPUs, said monitor means generating an error signal if predetermined criteria of the verifying or comparing function have not been met.

12. In a computer system having fault recoverable capability according to claim 11, wherein said monitor means further comprise:

logic means, operatively connected to said processing means, memory means, and protected memory means, for reinitializing said DPU in response to a recovery control signal.

13. In a computer system having fault recoverable capability according to claim 9, wherein said monitor means further comprise:

logic means, operatively connected to said processing means, memory means, and protected memory means, for reinitializing said DPU in response to a recovery control signal.

14. In a computer system having fault recoverable capability according to claim 12, wherein said monitor means includes at least one specific processing means, said specific processing means being less complex than said processing means.