Signal processing apparatus having first and second registers enabling both to concurrently receive identical information in one context and disabling one to retain the information in a next context
First Claim
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1. A signal processing apparatus comprising:
- an analog-to-digital converter for producing a digital signal corresponding to an analog input by a conversion process and for producing an interrupt signal when a conversion is complete;
a digital processing device havinga memory; and
a processor connecting to said analog-to-digital converter and responsive to said interrupt signal for entering the digital signal into the memory in alternative processing contexts identified by a state of said interrupt signal; and
said processor including;
a multiplier;
an arithmetic logic unit;
a plurality of register sets, each of said register sets having a first and second register, said first and second registers connected to concurrently store identical information during one of the processing contexts, said first register connected to individually participate and be continuously available in a next of the processing contexts when said first register is selected thereby enabling the second register to retain said information from said one processing context; and
a context switching circuit responsive to the state of said interrupt signal and connected to said first and second registers to alternatively control input and output operations of said register set to and from said multiplier and arithmetic logic unit depending on the processing context.
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Abstract
A signal processing apparatus includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.
186 Citations
10 Claims
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1. A signal processing apparatus comprising:
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an analog-to-digital converter for producing a digital signal corresponding to an analog input by a conversion process and for producing an interrupt signal when a conversion is complete; a digital processing device having a memory; and a processor connecting to said analog-to-digital converter and responsive to said interrupt signal for entering the digital signal into the memory in alternative processing contexts identified by a state of said interrupt signal; and said processor including; a multiplier; an arithmetic logic unit; a plurality of register sets, each of said register sets having a first and second register, said first and second registers connected to concurrently store identical information during one of the processing contexts, said first register connected to individually participate and be continuously available in a next of the processing contexts when said first register is selected thereby enabling the second register to retain said information from said one processing context; and a context switching circuit responsive to the state of said interrupt signal and connected to said first and second registers to alternatively control input and output operations of said register set to and from said multiplier and arithmetic logic unit depending on the processing context. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A signal processing apparatus with context switching including:
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an analog-to-digital converter for producing a digital signal responsive to an input analog signal and an interrupt signal indicating that the digital signal is available for processing; and a digital processing device having a processor for processing said digital signal in alternative processing contexts identified by a state of said interrupt signal; said processor including; a plurality of register sets, each of said register sets having a first and second register, said first and second registers connected to concurrently store identical information during one of the processing contexts, said first register connected to individually participate and be continuously available in a next of the processing contexts when said first register is selected thereby enabling the second register to retain said information from said one processing context; and a context switching circuit responsive to the state of said interrupt signal and connected to said first and second registers to alternatively control input and output operations of said register set to and from said processor depending on the processing context.
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Specification