Switch queue structure for one-network parallel processor systems

• US 5,313,649 A
• Filed: 05/28/1991
• Issued: 05/17/1994
• Est. Priority Date: 05/28/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Jackson, Rory D., Hsu, Yarsun
• Primary Examiner(s): Eng, David Y.
• Assistant Examiner(s): MOHAMED, AYNI Y
• Application Number:
  US07/706,136
• Time in Patent Office: 1,085 Days
• Field of Search: 395/200, 395/250, 395/800
• US Class Current: 710/317
• CPC Class Codes: G06F 15/17393 having multistage networks, e.g. broadcasting scattering, gathering, hot spot contention, combining/decombining
• CPC Class Codes: H04L 49/103 using a shared central buffer; using a shared memory
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 49/205 Quality of Service based
• CPC Class Codes: H04L 49/3018 Input queuing
• CPC Class Codes: H04L 49/3027 Output queuing
• CPC Class Codes: H04L 49/552 by ensuring the integrity of packets received through redundant connections
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

A switch queue structure for one-network parallel processor systems minimizes chip count and reduces the possibility of deadlock which might otherwise occur with this type of switch structure. The switch queue structure comprises a plurality of input ports and a plurality of output ports equal in number to a number of processor/memory elements (PMEs) in a parallel processor system. A plurality of identical stages interconnect the plurality of input ports and the plurality of output ports. Each stage includes a plurality of first groups of first-in, first-out (FIFO) registers storing request messages, a plurality of second groups of first-in, first-out registers storing response messages, and a plurality of multiplexers. Each of the multiplexers have inputs connected to the FIFO registers in each of the first and second groups for routing responses to memory requests from addressed processor/memory elements to requesting processor/memory elements and for routing memory requests from processor/memory elements to addressed processor/memory elements.

Claims

1. The tightly coupled parallel processor system recited in claim 1 wherein said plurality of identical stages are composed of a plurality of 2×

2 switches, each of said switches including four of said first-in, first-out registers of said first group and four of said first-in, first-out registers of said second group and two of said multiplexers, each of said multiplexers having two inputs connected to two of said first-in, first-out registers of said first group and two of said first-in, first-out registers of said second group.

2. The tightly coupled parallel processor system recited in claim 1 wherein inputs from said first group of first-in, first-out registers have a higher priority than inputs from said second group of first-in, first-out registers thereby reducing the possibility of deadlock.

3. The tightly coupled parallel processor system recited in claim 2 wherein priority within said first and second groups of first-in, first-out registers is assigned on a round-robin basis.

4. The tightly coupled parallel processor system recited in claim 3 wherein each switch further includes:

two input buffers connected to buffer messages to two first-in, first-out registers of each of said first and second groups of first-in, first-out registers; and

two output buffers connected to outputs of said two multiplexers to buffer messages from selected ones of said fist-in, first-out registers in each of said first and second groups of first-in, first-out registers.