Method for testing integrated circuits

• US 5,315,241 A
• Filed: 09/18/1991
• Issued: 05/24/1994
• Est. Priority Date: 09/18/1991
• Status: Expired due to Fees

• Current Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Original Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Inventors: Ewers, Charles R.
• Primary Examiner(s): NGUYEN, VINH P
• Application Number:
  US07/761,728
• Time in Patent Office: 979 Days
• Field of Search: 324/73.1, 324/158 R, 324/537, 357/45, 437/8, 257/48, 29/574
• US Class Current: 438/15
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06

Abstract

A substrate is provided as a test fixture for burning-in and testing integrated circuit devices. The substrate contains a plurality of unpackaged integrated circuit dice arranged in a regular matrix of rows and columns. The substrate is partitioned into an array of rectangles which can be easily broken apart. One integrated circuit die is attached in each rectangle. The integrated circuits are bonded to conductive traces in their respective rectangular areas, and the conductive traces are connected to common locations at one side of the substrate. Voltages can be applied to all of the devices simultaneously by contacting the common locations at the edge of the substrate. This allows for burn-in of all integrated circuit devices on the substrate in parallel, after which they can be separated and used individually on printed circuit boards.

Claims

1. A method for testing integrated circuit devices, comprising the steps of:

attaching a plurality of integrated circuit dice, containing a desired plurality of devices, to an insulating substrate having conductive traces on an upper surface and a lower surface thereof,

wherein said insulating substrate is divided into a plurality of regions defined by multiple lines of conductive through holes therethrough,

and wherein said conductive traces on said upper surface are electrically connected to said conductive traces on said lower surface through said through holes;

wire bonding to connect bonding wires from conductive bond pads on said integrated circuit dice to corresponding bonding locations on said traces on said upper surface;

providing electrical power and signals to said integrated circuit dice through said conductive traces on said lower surface, wherein the signals are connected to said integrated circuit dice through said through holes, said conductive traces on said upper surface, and said bonding wires, for at least a predetermined burn-in period;

physically breaking said conductive traces to at least partially isolate said integrated circuit dice; and

testing said integrated circuit dice.

2. The method of claim 1, further comprising the steps of:

before said electrical power providing step, applying a protective covering over the integrated circuit dice.

3. The method of claim 1, further comprising the steps of:

after said testing step, breaking the substrate along the linear series of through holes separating the substrate regions to provide a plurality of secondary substrates each containing one integrated circuit die.

4. The method of claim 1, wherein said insulating substrate consists essentially of alumina.

5. The method of claim 1, wherein said attaching step uses epoxy.

6. A method of testing integrated circuits, comprising the steps of:

affixing individual integrated circuits to respective portions of a breakable insulating substrate having conductive traces thereon;

wire-bonding electrical contact pads of each of said integrated circuits to respective ones of said traces;

burning-in said integrated circuits while supplying power through said traces;

physically severing at least some ones of said traces, to at least partially isolate said integrated circuits;

electrically testing said integrated circuits;

breaking apart said insulating substrate, to sever said traces and provide multiple fragments having respective ones of said integrated circuits thereon; and

packaging at least some ones of said integrated circuits with respective fragments of said insulating substrate still adhered thereto.

7. The method of claim 6, wherein said insulating substrate consists essentially of alumina.

8. The method of claim 6, wherein said affixing step uses epoxy.

9. The method of claim 6, further comprising the additional step of encapsulating said integrated circuit on said substrate, after said step of electrically testing.

10. The method of claim 6, further comprising the subsequent step of affixing said fragments of said substrate to a respective primary substrate.

11. A method of testing integrated circuits, comprising the steps of:

affixing individual integrated circuits to respective portions of a breakable insulating substrate having conductive traces thereon, and conductive through-holes positioned to define breakage lines;

wire-bonding electrical contact pads of each said integrated circuit to respective ones of said traces;

burning-in said integrated circuits while supplying power through said traces;

physically severing at least some ones of said traces, to at least partially isolate said integrated circuits;

electrically testing said integrated circuits;

breaking apart said insulating substrate, to sever said traces and provide multiple fragments having respective ones of said integrated circuits thereon; and

forming electrical connections to said through-holes of said fragments, to thereby form electrical connections to said contact pads of said integrated circuits.

12. The method of claim 11, wherein said insulating substrate consists essentially of alumina.

13. The method of claim 11, wherein said affixing step uses epoxy.

14. The method of claim 11, further comprising the additional step of encapsulating said integrated circuit on said substrate, after said step of electrically testing.

15. The method of claim 11, further comprising the additional step, prior to said step of forming electrical connections, of affixing said fragments of said substrate to a respective primary substrate.

16. A method of testing integrated circuits, comprising the steps of:

affixing individual integrated circuits to respective portions of a breakable insulating substrate having conductive traces thereon, and conductive through-holes positioned to define breakage lines;

wire-bonding electrical contact pads of each said integrated circuit to respective ones of said traces;

burning-in said integrated circuits while supplying power through said traces;

breaking off an edge portion of said substrate to physically sever at least some ones of said traces, to at least partially isolate said integrated circuits;

electrically testing said integrated circuits;

breaking apart said insulating substrate, to sever said traces and provide multiple fragments having respective ones of said integrated circuits thereon; and

forming electrical connections to said through-holes of said fragments, to thereby form electrical connections to said contact pads of said integrated circuits.

17. The method of claim 16, wherein said insulating substrate consists essentially of alumina.

18. The method of claim 16, wherein said affixing step uses epoxy.

19. The method of claim 16, further comprising the additional step of encapsulating said integrated circuit on said substrate, after said step of electrically testing.

20. The method of claim 16, further comprising the additional step, prior to said step of forming electrical connections, of affixing said fragments of said substrate to a respective primary substrate.