Phase-locked loop system with compensation for data-transition-dependent variations in loop gain

• US 5,315,270 A
• Filed: 08/28/1992
• Issued: 05/24/1994
• Est. Priority Date: 08/28/1992
• Status: Expired due to Term

• Current Assignee: American Telephone & Telegraph Company (AT&T, Inc.)
• Original Assignee: AT&T, Inc.
• Inventors: Leonowich, Robert H.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US07/936,824
• Time in Patent Office: 634 Days
• Field of Search: 331/1 A, 331/11, 331/16, 331/17, 331/25
• US Class Current: 331/1.00A
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/107 using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
• CPC Class Codes: H03L 7/1072 by changing characteristics of the charge pump, e.g. changing the gain

Abstract

The loop gain of a phase locked loop is made to be controllably responsive to the transition density of an input data signal. In one embodiment a charge pump, positioned between the phase detector and the loop filter, supplies pulse-amplitude-modulated current pulses to the loop filter, the amplitude of pulses being related to the data transition density.

Claims

1. In a phase-locked loop system for locking a clock signal to an input data signal, a method characterized by the steps of:

(a) counting the number of clock signal transitions which occur between data signal transitions, and

(b) altering the loop gain of said system in response to said counting step (a) by injecting a current pulse into the loop only at said data transitions.

2. The method of claim 1 wherein in step (b) the average loop gain is maintained essentially constant with changes in transition density of the input signal.

3. The method of claim 1 wherein said system includes a phase detector for comparing the phase of said input signal to that of said clock signal and wherein step (b) includes altering the effective gain of said phase detector, in response to said counting step (a).

4. The method of claim 3 wherein said system includes a loop filter for filtering the output of said phase detector and wherein step (b) includes injecting current pulses into said loop filter, the amplitude of said pulses being related to the number of said transitions counted in step (a).

5. The method of claim 4 wherein said injecting step includes using the output of said phase detector to determine when said current pulse are injected into said loop filter.

16. The method of claim 1 wherein the amplitude of said pulses is related to said number of clock transitions, wherein said data and clock signals are out of phase by an amount Δ

, and wherein in the width of said pulses is related to Δ

.

6. A method of locking a clock signal to an input data signal in a phase-locked loop, comprising the steps of:

(a) generating said clock signal,

(b) comparing the phase of said data signal with that of said clock signal to generate a first control signal, said comparing step having a characteristic gain measured in volts per radian,

(c) modulating the frequency of said clock signal in response to said first control signal, characterized by the steps of;

(d) counting the number of rising (or falling) clock signal transitions which occur between adjacent data signal transitions, and

(e) altering said gain in response to said counting step by injecting a current pulse into said loop only at said data transactions.

7. The method of claim 6 wherein, in step (e) the gain is altered in a manner to maintain it essentially constant with changes in the transition density of said input signal.

8. The method of claim 6 wherein step (e) includes

generating current pulses in response to said first control signal, the amplitudes of said pulses being related to the numbers counted in step (d), and the modulation of said clock signal frequency in step (c) being responsive to said current pulses.

17. The method of claim 6 wherein the amplitude of said pulses is related to said number of clock transitions, wherein said data and clock signals are out of phase by an amount Δ

, and wherein the width of said pulses is related to Δ

.

9. A data system comprising

a phase-locking loop subsystem for locking a clock signal to an input data signal, said loop subsystem having a characteristic loop gain related to the difference Δ

in phase between said input signal and said clock signal, and

a modulator for altering said loop gain in response to the difference between the data transition density of said input signal and that of said clock signal,

said modulator including a charge pump which injects a current pulse into said loop only at said data transitions.

10. The system of claim 9 wherein said modulator alters the loop gain in a manner to maintain said gain essentially constant with changes in the density of said input signal.

11. The system of claim 9 wherein said modulator includes a comparator for generating a first control signal related to said difference in data transition density, and

a source for injecting current pulses into said loop in response to said first control signal.

12. The system of claim 11 wherein

said comparator counts the number of rising (or falling) clock signal transitions between adjacent data signal transitions, and

said source injects pulses the amplitudes of which are related to said numbers counted by said comparator.

13. The system of claim 12 wherein

said loop subsystem includes a tri-state phase detector for generating second control signals responsive to the difference in phase between said input signal and said clock signal, and

the timing of the injection of said pulses is responsive to said second control signals generated by said phase detector.

14. The system of claim 13 wherein

said loop subsystem comprises an oscillator for generating said clock signal, a loop filter for providing a filtered third control signal for altering the frequency of said oscillator, and said source supplies said current pulses to said filter so as to generate said third control signal.

18. The method of claim 9 wherein the magnitude of said pulses is related to the number of clock transitions which occur between data transitions, and wherein the width of said pulses is related to Δ

.

15. A phase-locked loop subsystem for locking a clock signal to an input data signal comprising

an oscillator for generating said clock signal in response to a first control signal,

a phase detector for comparing the phase of said input signal with that of said clock signal and for generating second control signals in response to a phase difference Δ

between said signals,

a comparator for counting the number of rising (or falling) clock signal transitions which occur between adjacent data signal transitions to generate third control signals, the durations of said third control signals being related to said numbers,

a low pass filter, the output of said filter providing said first control signal to said oscillator, and

a current source for injecting amplitude modulated current pulses into said filter only at said data transitions, the timing of said pulses being responsive to said second control signals from said phase detector, and the amplitude of said pulses being responsive to said third control signals from said comparator and being effective to maintain the loop gain essentially constant with changes in the transition density of said input signal

the amplitude of each said pulses being related to said number of clock signal transitions and the width of each of said pulses being related to Δ

.