Multiple serial access memory for use in feedback systems such as motion compensated television

• US 5,315,388 A
• Filed: 11/19/1991
• Issued: 05/24/1994
• Est. Priority Date: 11/19/1991
• Status: Expired due to Term

• Current Assignee: General Instrument Corporation (CommScope Holding Company, Inc.)
• Original Assignee: General Instrument Corporation (CommScope Holding Company, Inc.)
• Inventors: Shen, Paul, Krause, Edward A., Paik, Woo H.
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Harvey, David E.
• Application Number:
  US07/791,369
• Time in Patent Office: 917 Days
• Field of Search: 365/230.03, 365/230.05, 365/219, 365/221, 365/189.02, 365/189.01, 365/189.12, 365/230, 365/09, 358/22, 358/160, 358/167, 358/36, 358/105, 358/21 R, 340/799, 340/800, 340/801, 382/41, 382/42, 382/44
• US Class Current: 348/718
• CPC Class Codes: G11C 7/1036 using data shift registers
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/433 characterised by techniques for memory access
• CPC Class Codes: H04N 19/51 Motion estimation or motion compensation
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

A multiple serial access memory which includes a dynamic random access memory array is disclosed. The array is randomly addressed to input blocks of data. Address signals are provided to the array to output rows of data. A plurality of serial output ports are coupled to the output of the array for selectively latching different rows of data output from the array. The serial output ports are clocked to output the latched data therefrom. In an illustrated embodiment, each of the serial output ports contains a shift register having a length equal to the width of the memory array. The shift register is responsive to a first timing signal for latching a row of data from the array. A second timing signal actuates the shift register to shift a row of latched data. The serial access selector coupled to the shift register outputs a selected portion of the shifted data from the serial output port. The serial access memory has particular application as the frame store for a motion compensated interframe image coding/decoding system.

Claims

1. A multiple serial access memory comprising:

a dynamic random access memory array P rows high by Q columns wide by B bits deep;

means for addressing said array to randomly input N row high by M column wide blocks of B bit data bytes thereto, where N<

P and M<

Q;

means for outputting rows of data of length L from said array in response to address signals provided by said addressing means, where M<

L<

Q;

a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means; and

means for clocking said serial output ports to output latched data therefrom.

2. A memory in accordance with claim 1 further comprising:

timing means operatively associated with said array for limiting access to said array to one of said serial output ports at a time.

3. A memory in accordance with claim 1 wherein each of said serial output ports comprises:

a shift register having a length at least equal to a width of said array, said shift register being responsive to a first signal from a timing means for latching a row of data from said array and responsive to a second signal from said timing means for shifting the row of latched data; and

a serial access selector coupled to said shift register for outputting a selected portion of the shifted data from the serial output port.

4. In a digital television apparatus that requires memory for storing a set of working data and memory for storing a set of display data derived from said working data, the improvement comprising:

a dynamic random access memory array P rows high by Q columns wide by B bits deep;

means for addressing said array to randomly input N row high by M column wide blocks of B bit data bytes thereto, where N<

P and M<

Q;

means for outputting rows of data of length L from said array in response to address signals provided by said addressing means, where M<

L<

Q;

a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means; and

means for clocking said serial output ports to output latched data therefrom;

wherein at least one of said serial output ports is used to output working data from said array and at least one other of said serial output ports is used to output display data from said array.

5. Television apparatus in accordance with claim 4 further comprising:

timing means operatively associated with said array for limiting access to said array to one of said serial output ports at a time.

6. Television apparatus in accordance with claim 4 wherein each of said serial output ports comprises:

a shift register having a length at least equal to a width of said array, said shift register being responsive to a first signal from a timing means for latching a row of data from said array and responsive to a second signal from said timing means for shifting the row of latched data; and

a serial access selector coupled to said shift register for outputting a selected portion of the shifted data from the serial output port.

7. Television apparatus in accordance with claim 4 wherein:

said working data is provided from the array to its respective serial output port in one of a field format and frame format; and

said display data is provided from the array to its respective serial output port in the other of said field format and frame format.

8. Television apparatus in accordance with claim 4 wherein:

said working data is provided from the array to its respective serial output port in an NxM block format, where N is a plurality of television lines and M is a number of pixels less than the number of pixels contained in a full television line; and

said display data is provided from the array to its respective serial output port in a television line format.

9. Television apparatus in accordance with claim 4 wherein:

said display data comprises pixel data for a current video frame;

said working data comprises pixel data from a previous video frame for use in reconstructing a current video frame from a motion compensation difference signal;

said array has a storage capacity sufficient to store said current video frame together with enough working data to accommodate a predetermined motion estimation search area; and

said array is filled with data for successive video frames on an ongoing basis with the data for a current frame overwriting a portion of the data for a previous frame that precedes a current motion estimation search area.

10. A method for storing video data for use by a motion compensator including a motion estimator that estimates motion over a maximum horizontal displacement DX and a maximum vertical displacement DY, comprising the steps of:

providing a frame store memory for storing N+K lines of video data, where N is the number of lines in a video frame and K is at least equal to the number of lines corresponding to the maximum vertical displacement DY of the motion estimator; and

filling said frame store memory with video data from successive video frames on a revolving basis, wherein N consecutive lines of a second video frame are written into said memory following the last line of a first video frame, such that the first video frame is overwritten by the second video frame on a first-in first-out basis, with the last K lines of the first video frame remaining in said memory once the full second video frame has been written into said memory.

11. A multiple serial access memory comprising:

a dynamic random access memory array;

means for addressing said array to input data thereto and output data therefrom;

means for outputting rows of data from said array in response to address signals provided by said addressing means;

a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means; and

means for clocking said serial output ports to output latched data therefrom;

wherein each of said serial output ports comprises;

a shift register having a length at least equal to a width of said array, said shift register being responsive to a first signal from a timing means for latching a row of data from said array and responsive to a second signal from said timing means for shifting the row of latched data; and

a serial access selector coupled to said shift register for outputting a selected portion of the shifted data from the serial output port.

12. A memory in accordance with claim 11 further comprising:

timing means operatively associated with said array for limiting access to said array to one of said serial output ports at a time.

13. In a digital television apparatus that requires memory for storing a set of working data and memory for storing a set of display data derived from said working data, the improvement comprising:

a dynamic random access memory array;

means for addressing said array to input data thereto and output data therefrom;

means for outputting rows of data from said array in response to address signals provided by said addressing means;

a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means; and

means for clocking said serial output ports to output latched data therefrom;

wherein at least one of said serial output ports is used to output working data from said array and at least one other of said serial output ports is used to output display data from said array and each of said serial output ports comprises;

a shift register having a length at least equal to a width of said array, said shift register being responsive to a first signal from a timing means for latching a row of data from said array and responsive to a second signal from said timing means for shifting the row of latched data; and

a serial access selector coupled to said shift register for outputting a selected portion of the shifted data from the serial output port.

14. A memory in accordance with claim 13 further comprising:

timing means operatively associated with said array for limiting access to said array to one of said serial output ports at a time.

15. In a digital television apparatus that requires memory for storing a set of working data and memory for storing a set of display data derived from said working data, the improvement comprising:

a dynamic random access memory array;

means for addressing said array to input data thereto and output data therefrom;

means for outputting rows of data from said array in response to address signals provided by said addressing means;

a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means;

means for clocking said serial output ports to output latched data therefrom;

at least one of said serial output ports being used to output working data from said array; and

at least one other of said serial output ports being used to output display data from said array;

wherein;

said working data is provided from the array to its respective serial output port in one of a field format and frame format; and

said display data is provided from the array to its respective serial output port in the other of said field format and frame format.

16. A memory in accordance with claim 15 further comprising:

timing means operatively associated with said array for limiting access to said array to one of said serial output ports at a time.

17. In a digital television apparatus that requires memory for storing a set of working data and memory for storing a set of display data derived from said working data, the improvement comprising:

a dynamic random access memory array;

means for addressing said array to input data thereto and output data therefrom;

means for outputting rows of data from said array in response to address signals provided by said addressing means;

a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means;

means for clocking said serial output ports to output latched data therefrom;

at least one of said serial output ports being used to output working data from said array; and

at least one other of said serial output ports being used to output display data from said array;

wherein;

said working data is provided from the array to its respective serial output port in an NxM block format, where N is a plurality of television lines and M is a number of pixels less than the number of pixels contained in a full television line; and

said display data is provided from the array to its respective serial output port in a television line format.

18. A memory in accordance with claim 17 further comprising:

timing means operatively associated with said array for limiting access to said array to one of said serial output ports at a time.

19. In a digital television apparatus that requires memory for storing a set of working data and memory for storing a set of display data derived from said working data, the improvement comprising:

a dynamic random access memory array;

means for addressing said array to input data thereto and output data therefrom;

means for outputting rows of data from said array in response to address signals provided by said addressing means;

a plurality of serial output ports coupled to said outputting means for selectively latching rows of data output by said outputting means;

means for clocking said serial output ports to output latched data therefrom;

at least one of said serial output ports being used to output working data from said array; and

at least one other of said serial output ports being used to output display data from said array;

wherein;

said display data comprises pixel data for a current video frame;

said working data comprises pixel data from a previous video frame for use in reconstructing a current video frame from a motion compensation difference signal;

said array has a storage capacity sufficient to store said current video frame together with enough working data to accommodate a predetermined motion estimation search area; and

said array is filled with data for successive video frames on an ongoing basis with the data for a current frame overwriting a portion of the data for a previous frame that precedes a current motion estimation search area.

20. A memory in accordance with claim 19 further comprising:

timing means operatively associated with said array for limiting access to said array to one of said serial output ports at a time.