Hermetically packaged HDI electronic system

• US 5,315,486 A
• Filed: 06/07/1993
• Issued: 05/24/1994
• Est. Priority Date: 12/16/1991
• Status: Expired due to Fees

• Current Assignee: Martin Marietta Corporation
• Original Assignee: General Electric Company
• Inventors: Bernard, Edward S., Kornrumpf, William P., Fillion, Raymond A.
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): SPARKS, DONALD ALAN
• Application Number:
  US08/073,250
• Time in Patent Office: 351 Days
• Field of Search: 257/668, 257/684, 257/700, 257/723, 257/724, 257/758, 257/759, 257/760, 257/782, 257/676, 257/688, 361/760, 361/761, 361/762, 361/763, 361/764, 361/792, 361/793, 361/794, 361/772, 361/774, 361/807, 361/809, 361/813, 437/206, 437/207, 437/217, 437/220, 439/70, 174/52.4, 174/253, 174/255, 174/260, 174/261
• US Class Current: 361/795
• CPC Class Codes: H01L 2224/2402 Laminated, e.g. MCM-L type
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/057 the leads being parallel to the base
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A hermetic package particularly adapted for high density interconnect (HDI) electronic systems employs a ceramic substrate which serves as a base for the hermetic package. The substrate comprises a cofired body including buried conductors which provide electrical continuity between a set of inner contact points and a set of outer contact points bridging a seal ring that comprises either a solder seal or a weldable seal for the hermetic package lid. The outer contact points may be directly connected to a leadframe. The leadframe leads, after severing, can be directly attached to a printed circuit board.

Claims

1. A packaged electronic system comprising:

a ceramic substrate having a component-supporting surface, and at least one electronic component disposed on said component-supporting surface, said component having contact pads thereon;

a seal ring disposed on said component-supporting surface encircling said at least one electronic component;

a set of inner contact points on said component-supporting surface located inside said seal ring, and a corresponding set of outer contact points on said component-supporting surface located outside said seal ring;

a set of electrical conductors at least in part buried in said ceramic substrate and extending between said inner and outer sets of contact points;

electrical connections between at least some of said components contact pads and said inner contact points, comprising a multilayer interconnect structure including interleaved layers of dielectric material and conductive material disposed over portions of said substrate, over said at least one electronic component and over said inner set of contact points; and

a package lid attached to said seal ring and enclosing said at least one electronic component and said electrical connections.

2. The packaged electronic system in accordance with claim 1, wherein said ceramic substrate and said set of electrical conductors buried at least in part in said ceramic substrate comprise a cofired body.

3. The packaged electronic system in accordance with claim 1, wherein said component-supporting surface includes at least one cavity, said electronic component being disposed in said cavity such that a major surface of said electronic component is substantially coplanar with a portion of said component-supporting surface surrounding said cavity.

4. The packaged electronic system in accordance with claim 1 and further including a lead frame, at least some of said outer contact points being connected to corresponding individual leads of said lead frame.

5. A packaged electronic system comprising:

a ceramic substrate having a component-supporting surface, and at least one electronic component disposed on said component-supporting surface, said component having contact pads thereon;

a seal ring disposed on said component-supporting surface encircling said at least one electronic component;

a set of inner contact points on said component-supporting surface located inside said seal ring, and a corresponding set of outer contact points on said component-supporting surface located outside said seal ring;

a set of electrical conductors at least in part buried in said ceramic substrate and extending between said inner and outer sets of contact points;

electrical connections between at least some of said component contact pads and said inner contact points;

a package lid attached to said seal ring and enclosing said at least one electronic component and said electrical connections; and

an electrical feedthrough extending from said seal ring through said ceramic substrate to an opposite surface thereof, whereby said seal ring and said package lid may be grounded through said electrical feedthrough.

6. The packaged electronic system in accordance with claim 5, wherein said ceramic substrate, said set of electrical conductors buried at least in part in said ceramic substrate and said electrical feedthrough comprise a cofired body.

7. A packaged electronic system in accordance with claim 5, wherein said ceramic substrate and said set of electrical conductors at least in part buried in said ceramic substrate comprise a cofired body.

8. A packaged electronic system in accordance with claim 5, wherein said outer contact points are adapted for connection to individual leads of a lead frame.

9. A packaged electronic system comprising:

a ceramic substrate having a component-supporting surface which includes at least one cavity, and a plurality of electronic components, each of said components having contact pads thereon, disposed within said at least one cavity on said component-supporting surface such that major surfaces of said components are substantially coplanar with portions of said component-supporting surface surrounding said at least one cavity;

a seal ring disposed on said component-supporting surface encircling said at least one electronic component;

a set of inner contact points on said component-supporting surface located inside said seal ring, and a corresponding set of outer contact points on said component-supporting surface located outside said seal ring;

a set of electrical conductors at least in part buried in said ceramic substrate and extending between said inner and outer sets of contact points;

electrical connections between at least some of said component contact pads and said inner contact points; and

a package lid attached to said seal ring and enclosing said at least one electronic component and said electrical connections.

10. The packaged electronic system in accordance with claim 9, wherein said electrical connections extending between at least some of said component contact pads and at least some of said inner contact points, respectively, comprise a multilayer interconnect structure including interleaved layers of dielectric material and conductive material, said multilayer interconnect structure being disposed over said portion of said component-supporting surface surrounding said cavity, over said electronic components and over said inner set of contact points.

11. A packaged electronic system in accordance with claim 9, wherein said ceramic substrate and said set of electrical conductors at least in part buried in said ceramic substrate comprise a cofired body.

12. A packaged electronic system in accordance with claim 9, wherein said outer contact points are adapted for connection to individual leads of a lead frame.

13. A packaged electronic system comprising:

a ceramic substrate having a component-supporting surface including at least one cavity, and at least one electronic component, having contact pads thereon, and disposed within said at least one cavity such that a major surface of said at least one electronic component is substantially coplanar with portions of said component-supporting surface surrounding said at least one cavity;

a solder seal ring on said portions of said component-supporting surface surrounding said at least one cavity;

a set of inner contact points on said component-supporting surface located inside said seal ring, and a corresponding set of outer contact points on said component-supporting surface located outside said seal ring;

a set of electrical conductors at least in part buried in said ceramic substrate and extending between said inner and outer sets of contact points;

electrical connections between at least some of said component contact pads and said inner contact points; and

a package lid attached to said seal ring and enclosing said at least one electronic component and said electrical connections.

14. A packaged electronic system in accordance with claim 13, wherein said ceramic substrate and said set of electrical conductors at least in part buried in said ceramic substrate comprise a cofired body.

15. A packaged electronic system in accordance with claim 13, wherein said outer contact points are adapted for connection to individual leads of a lead frame.

16. A packaged electronic system comprising:

a ceramic substrate having a component-supporting surface including at least one cavity;

at least one electronic component having contact pads therein and disposed in said cavity such that a major surface of said electronic component is substantially coplanar with a portion of said component-supporting surface surrounding said cavity;

said component-supporting surface including a peripheral ledge having a ledge surface recessed with respect to said portion of said component-supporting surface surrounding said cavity;

a seal ring comprising a weldable ring disposed on said ledge surface encircling said at least one electronic component, said weldable ring having a thickness such that a major surface thereof is substantially coplanar with said portion of said component-supporting surface surrounding said cavity;

a set of inner contact points on said component-supporting surface and a corresponding set of outer contact points on said component-supporting surface, said inner contact points being encircled by said seal ring and said outer contact points being situated outside said seal ring;

a set of electrical conductors buried at least in part in said ceramic substrate and extending between said inner and outer sets of contact points;

electrical connections extending between at least some of said component contact pads and at least some of said inner contact points, respectively; and

package lid attached to said seal ring and enclosing said electronic component and said electrical connections.

17. A hermetically packaged electronic system comprising:

a package base comprising a nonconductive substrate having a component-supporting surface;

a plurality of electronic components disposed on said components-supporting surface;

a seal ring disposed on said component-supporting surface encircling said electronic components;

a set of inner contact points on said component-supporting surface and a corresponding set of outer contact points on said component-supporting surface, said inner contact points being encircled by said seal ring and said outer contact points being situated outside said seal ring;

a set of electrical conductors buried at least in part in said substrate and extending between said inner and outer sets of contact points;

a multilayer interconnect structure including interleaved layers of dielectric material and conductive material, said multilayer interconnect structure being disposed over said components, over portions of said substrate, and over said inner set of contact points; and

a package lid hermetically attached to said seal ring and enclosing said electronic components and said multilayer interconnect structure.

18. The hermetically packaged electronic system in accordance with claim 17 and further comprising an electrical feedthrough extending from said seal ring through said substrate to a surface opposite said component-supporting surface, said feedthrough allowing said seal ring and said package lid to be grounded therethrough.

19. The hermetically packaged electronic system in accordance with claim 17 and further including a lead frame, at least some of said outer contact points being connected to corresponding individual leads of said lead frame.

20. The hermetically packaged electronic system in accordance with claim 17, wherein

said component-supporting surface includes at least one cavity, said electronic components being disposed in said cavity such that major surfaces of said electronic components are substantially coplanar with a portion of said component-supporting surface surrounding said cavity;

and wherein

said seal ring comprises a solder seal ring on said portion of said component-supporting surface surrounding said cavity.

21. The hermetically packaged electronic system in accordance with claim 17, wherein

said component-supporting surface includes at least one cavity, said electronic components being disposed in said cavity such that major surfaces of said electronic components are substantially coplanar with a portion of said component-supporting surface surrounding said cavity and said component-supporting surface further includes a peripheral ledge having a ledge surface recessed with respect to said portion of said component-supporting surface surrounding said cavity;

and wherein

said seal ring comprises a weldable ring disposed on said ledge surface, said weldable ring having a thickness such that a major surface thereof is substantially coplanar with said portion of said component-supporting surface surrounding said cavity.