Segmented column memory array

• US 5,315,541 A
• Filed: 07/24/1992
• Issued: 05/24/1994
• Est. Priority Date: 07/24/1992
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SunDisk Corporation (Seagate Technology Holdings Plc)
• Inventors: Harari, Eliyahou, Mehrotra, Sanjay
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): ZARABIAN, AMIR
• Application Number:
  US07/919,715
• Time in Patent Office: 669 Days
• Field of Search: 365/63, 365/51, 365/185, 365/182
• US Class Current: 365/185.13
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

In an array of solid-state memory cells organized into rows and segmented columns and addressable by wordlines and bit lines, a memory cell within a segmented column is addressable by segment-select transistors which selectively connect the memory cell'"'"'s pair of bit lines via conductive lines running parallel to the columns to a column decode circuit. The disposition of the segment-select transistors and the conductive lines relative to the segmented columns enables one segment-select transistor to fit in every two or more columns. In one embodiment, the segment-select transistors have double the pitch of the columns while the conductive lines have the same pitch of the columns. In another embodiment, the segment-select transistor have four times the pitch of the columns while the conductive lines have double the pitch of the columns. This enables the use of larger size segment-select transistors which are necessary for passing higher currents in devices such as EPROM or flash EEPROM. Column segmentation effectively isolates defects to individual segments and reduces the capacitance in the source and drain of an address memory cell.

Claims

1. In an EPROM or EEPROM of Flash EEPROM integrated circuit memory device, including a two-dimensional array of memory cells organized in rows and columns, each memory cell having a gate, a source and a drain, said two-dimensional array having a word line connected to all the gates in each row, said integrated circuit memory device comprising:

a plurality of segmented arrays formed by partitioning the two-dimensional array along the column direction, each segmented array being formed by a bank of segmented columns and each segmented column having a pair of independent segmented bit lines connected respectively to all the sources and drains therein, such that each segmented array is addressable column-by-column by an array of segmented bit lines;

cell accessing means connectable to an addressed cell in a segmented array by the word line and the pair of segmented bit lines connected thereto, said cell accessing means further comprising;

a plurality of electrically isolated conductive rails parallel to and overlaying the columns of the two-dimensional array, such that for each segmented column therein, the pair of segmented bit lines thereof is associated with a corresponding pair of conductive rails for access therethrough;

first and second switching transistors for exclusively and switchably connecting the pair of segmented bit lines to the pair of corresponding conductive rails;

each first switching transistor located at a top end of each segmented column for switchably connecting first of the pair of segmented bit lines to first of the pair of corresponding conductive rails; and

said second switching transistor located at a bottom end of each segmented column for switchably connecting second of the pair of segmented bit lines to second of the pair of corresponding conductive rails;

thereby forming in each segmented array, a row of first switching transistors at a top end thereof one-to-one connected to one set of alternate segmented bit lines therein and a row of second switching transistors at a bottom end thereof one-to-one connected to a complement set of alternate segmented bit lines therein, each said row of first or second switching transistors having a pitch double that of the array of segmented bit lines.

2. An integrated circuit memory device as in claim 1, wherein said cell accessing means further comprises:

a contact pad for each of said first and second switching transistors to connect to a corresponding conductive rail, thereby forming first and second rows of contact pads respectively at the top and bottom ends of each segmented array, and respectively having a pitch equal to that of said row of first or second switching transistors.

3. An integrated circuit memory device as in claim 1, wherein:

each segmented array is a virtual ground memory array wherein along each row thereof the memory cells are serially interconnected by having the drain of one memory cell connected to the source of another memory cell adjacent thereto, such that a segmented bit line connected to all the drains of one segmented column coincides with that connected to all the sources of another segmented column adjacent thereto, and that for each segmented array, the segmented bit lines therein has a pitch equal to that of the bank of segmented columns thereof.

4. An integrated circuit memory device as in claim 3, wherein said cell accessing means further comprises:

a contact pad for each of said first and second switching transistors to connect to a corresponding conductive rail, thereby forming first and second rows of contact pads respectively at the top and bottom ends of each segmented array, and respectively having a pitch equal to that of said row of first or second switching transistors.

5. An integrated circuit memory device as in claim 4, wherein:

said plurality of conductive rails correspond one-to-one to the array of the segmented bit lines in the two-dimensional array, thereby having a pitch equal to that of the array of segmented bit lines.

6. An integrated circuit memory device as in claim 4, said plurality of segmented arrays being arranged along the column direction to form the two-dimensional array, and each segmented array therein having a top end and a bottom end thereof, wherein:

between each pair of adjacent segmented arrays therein, with a first of the pair immediately below a second of the pair, the first row of contact pads at the top end of the first coincides with the second row of contact pads at the bottom end of the second.

7. An integrated circuit memory device as in claim 4, wherein:

said plurality of conductive rails have a pitch double that of the segmented bit lines of a segmented array.

8. An integrated circuit memory device as in claim 7, said plurality of segmented arrays being arranged along the column direction to form the two-dimensional array, such that the segmented bit lines in each segmented array are aligned with that of corresponding segmented bit lines of other segmented arrays in the two-dimensional array, and each segmented array therein having a top end and a bottom end thereof, wherein:

for each cluster of three segmented arrays therein constituted from a lower, middle and upper segmented arrays, the segmented bit lines of the middle segmented array are alternately connected to that of the corresponding segmented bit lines of the upper segmented array and the lower segmented arrays at the second transistor to form a set of straddled segmented bit lines.

9. An integrated circuit memory device as in claim 8, wherein:

said set of straddled segmented bit lines is constituted from first and second sets of interleaving straddled segmented bit lines, said first set of interleaving straddled segmented bit lines being formed by every other straddled segmented bit lines in the full set of straddles segmented bit lines and said second set of interleaving straddles segmented bit lines being formed by the complement of said first set of interleaving segmented bit lines in said full set of straddled segmented bit lines; and

said first and second sets of interleaving straddled segmented bit lines being each grouped into pairs, each pair sharing a corresponding conductive rail for the straddled segmented bit lines therein to independently and switchably connectable thereto.

10. In an EPROM or EEPROM of Flash EEPROM integrated circuit memory device, including a two-dimensional array of memory cells organized in rows and columns, each memory cell having a gate, a source and a drain, said two-dimensional array having a word line connected to all the gates in each row, a method of isolating defects that may arise in said array comprising:

partitioning the two-dimensional array along the column direction to form a plurality of segmented arrays, each segmented array being formed by a bank of segmented columns and each segmented column having a pair of independent segmented bit lines connected respectively to all the sources and drains therein, such that each segmented array is addressable column-by-column by an array of segmented bit lines;

selectively connecting a cell accessing means to an addressed cell in a segmented array by the word line and the pair of segmented bit lines connected thereto, said cell accessing means further comprising;

a plurality of electrically isolated conductive rails parallel to and overlaying the columns of the two-dimensional array, such that for each segmented column therein, the pair of segmented bit lines thereof is associated with a corresponding pair of conductive rails for access therethrough;

first and second switching transistors for exclusively and switchably connecting the pair of segmented bit lines to the pair of corresponding conductive rails;

each first switching transistor located at a top end of each segmented column for switchably connecting first of the pair of segmented bit lines to first of the pair of corresponding conductive rails; and

each second switching transistor located at a bottom end of each segmented column for switchably connecting second of the pair of segmented bit lines to second of the pair of corresponding conductive rails;

thereby forming in each segmented array, a row of first switching transistors at a top end thereof one-to-one connected to one set of alternate segmented bit lines therein and a row of second switching transistors at a bottom end thereof one-to-one connected to a complement set of alternate segmented bit lines therein, each said row of first or second switching transistors having a pitch double that of the array of segmented bit lines; and

said two-dimensional array being segmented that a segmented column therein containing a defect is isolated therein.

11. In an EPROM or EEPROM of Flash EEPROM integrated circuit memory device, including a two-dimensional array of memory cells organized in rows and columns, each memory cell having a gate, a source and a drain, said two-dimensional array having a word line connected to all the gates in each row, a method of reducing capacitance in the source and drain of an adressed memory cell comprising:

partitioning the two-dimensional array along the column direction to form a plurality of segmented arrays, each segmented array being formed by a bank of segmented columns and each segmented column having a pair of independent segmented bit lines connected respectively to al the sources and drains therein, such that each segmented array is addressable column-by-column by an array of segmented bit lines;

selectively connecting a cell accessing means to an addressed cell in a segmented array by the word line and the pair of segmented bit lines connected thereto, said cell accessing means further comprising;

a plurality of electrically isolated conductive rails parallel to and overlaying the columns of the two-dimensional array, such that for each segmented column therein, the pair of segmented bit lines thereof is associated with a corresponding pair of conductive rails for access therethrough;

first and second switching transistors for exclusively and switchably connecting the pair of segmented bit lines to the pair of corresponding conductive rails;

each first switching transistor located at a top end of each segmented column for switchably connecting first of the pair of segmented bit lines to first of the pair of corresponding conductive rails; and

each second switching transistor located at a bottom end of each segmented column for switchably connecting second of the pair of segmented bit lines to second of the pair of corresponding conductive rails;

thereby forming in each segmented array, a row of first switching transistors at a top end thereof one-to-one connected to one set of alternate segmented bit lines therein and a row of second switching transistors at a bottom end thereof one-to-one connected to a complement set of alternate segmented bit lines therein, each said row of first or second switching transistors having a pitch double that of the array of segmented bit lines; and

said two-dimensional array having segmented arrays with independent segmented bit lines that additional capacitance imparted from other segmented bit lines is avoided.