Memory controller for nonvolatile RAM operation, systems and methods

• US 5,315,549 A
• Filed: 06/11/1991
• Issued: 05/24/1994
• Est. Priority Date: 06/11/1991
• Status: Expired due to Term

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Lee, Robert D., Scherpenberg, Francis A., Mumper, Eric W., Rea, John W.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US07/714,545
• Time in Patent Office: 1,078 Days
• Field of Search: 307/65, 307/66, 365/189.01, 365/189.09, 365/195, 365/229
• US Class Current: 365/189.09
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A memory controller for supplying backup battery power when a main power supply voltage drops together with programmable plus power fail write protection. The controller includes supravoltage induced sleep mode operation, MOS switching between backup batteries during backup operation based on battery voltage levels and discharge circuitry for battery disposal.

Claims

1. A memory controller, comprising:

(a) at least one address input node, said address input node(s) capable of inputting an address, said address having a set of write protected addresses and a set of stored data;

(b) a memory write input node;

(c) a memory write output node;

(d) at least one programmable element with first and second states, said programmable element(s) corresponding to said set of write protected addresses; and

(e) switch circuitry connected to said address input node(s), said memory write input node, said memory write output node, and said programmable element(s), said switch circuitry isolating said memory write output node from said memory write input node when said programmable element is in said first state and said address at said address input node(s) is in said set of write protected addresses, but said switch circuitry coupling said memory write output node to said memory write input node when said programmable element is in said second state and said address at said address input node(s) is in said set of write protected addresses.

2. The memory controller of claim 1, wherein:

(a) said programmable element(s) may be programmed by applying a specific sequence of signals at said address input node(s) and said memory write input node.

3. The memory controller of claim 1, wherein:

(a) addresses have N number of bits;

(b) said at least one address input node is K number of address input nodes

(c) said at least one programmable element is 2^K number of elements; and

(d) said corresponding sets of write protected addresses are blocks of addresses of size 2^N-K.

4. The memory controller of claim 3, wherein:

(a) said 2^K number of programmable elements may be programmed by applying a specific sequence of signals at said address input node(s) and a chip enable node.

5. The memory controller of claim 1, further comprising:

(a) a primary power input node with a voltage level at a first magnitude;

(b) a backup power input node with a voltage level at a second magnitude;

(c) a power output node;

(d) write prevention circuitry coupled to said primary power input node, and said write prevention circuitry isolating said memory write output node from said memory write input node when said first magnitude of the voltage level of said primary power input node decreases below a first level; and

(e) backup circuitry coupled to said backup power, input node, said primary power input node, and said power output node, said backup circuitry connecting said backup power input node to said power output node when said first magnitude of said voltage level at said primary power input node decreases to below said second magnitude of said voltage level at said backup power input node.

6. The memory controller of claim 5, wherein said first level is defined to be outside an approximate range of 4.5 volts to 6 volts or an approximate range of 4.75 volts to 6 volts and said first magnitude of said voltage level at said primary power input node is within an approximate range of 4.5 volts to 6 volts or within an approximate of 4.75 volts to 6 volts and said second magnitude of said voltage level at said backup power input node is within an approximate range of 2 volts to 4 volts.

7. The memory controller of claim 1, wherein a user controls which of said programmable element(s) are programmed.

8. An integrated circuit, comprising:

(a) a first input node;

(b) a second input node;

(c) a switch selectively coupling one of said first and second nodes to a third node;

(d) a first p-channel FET with source coupled to said first input node and gate coupled to said third node;

(e) a second p-channel FET with source coupled to said second input node and gate coupled to said third node; and

(f) circuitry connected to the drains of said first and second FETs to activate said switch if either of said FETs is turned on.

9. The integrated circuit of claim 8, wherein:

(a) said circuitry includes (i) a first impedance connected between said drain of said first FET and a reference node, (ii) a second impedance connected between said drain of said second FET and said reference node, and (iii) a latch with a first input coupled to said drain of said first FET and a second input coupled to said drain of said second FET, and with an output coupled to activate said switch; and

(b) said switch includes (i) a third FET coupled between said first input node and said third node and (ii) a fourth FET coupled between said second input node and said third node.

10. An integrated circuit, comprising:

(a) a power supply node capable of providing power;

(b) a backup power node capable of providing power;

(c) circuitry powered by power from either said power supply node or said backup power node, said power selected in accordance with the voltage level at said power supply node compared to the voltage level at said backup power node; and

(d) a programmable element that is programmed to a first state when the voltage level at said power supply node exceeds a first voltage level, wherein said circuitry operates (i) in a first mode if powered by power selected from said power supply node, (ii) in a second mode different from said first mode if powered by power selected from said backup power node and said programmable element is in said first state, and (iii) in a third mode different from said first and second modes if powered by power from said backup power node and said programmable element is not in said first state.

11. An integrated circuit, comprising:

(a) a power supply node;

(b) a battery power node;

(c) a reference voltage node;

(d) means for connecting said reference voltage node and selectively to either said power supply node or said battery power node; and

(e) a switch selectively coupling said battery power node to said reference node when said means for connecting said reference voltage node and selectively to either said power supply node or said battery power node is connected to said power supply node, said switch connected to a discharge node;

(f) wherein a signal at said discharge node controls said switch.

12. The integrated circuit of claim 11, further comprising:

(a) a second battery power node; and

(b) a second switch coupling said second battery power node to said reference voltage node when said means for connecting said reference voltage node and selectively to either said power supply node or said battery power node is connected to said power supply node, said second switch connected to said discharge node;

(c) wherein said signal at said discharge node controls said second switch.

13. The integrated circuit of claim 11, further comprising:

(a) at least one programmable element coupled to said discharge node, wherein said programmable element provides said signal at said discharge node.