Trenched DMOS transistor fabrication using six masks

• US 5,316,959 A
• Filed: 08/12/1992
• Issued: 05/31/1994
• Est. Priority Date: 08/12/1992
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, Ho, Yueh-Se, Owyang, King, Chang, Mike F., Kwan, Sze-Hon
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US07/928,909
• Time in Patent Office: 657 Days
• Field of Search: 437/40, 437/41, 437/67, 437/203, 257/328, 257/330, 257/334
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trenched DMOS transistor is fabricated using six masking steps. One masking step defines both the P+ regions and the active portions of the transistor which are masked using a LOCOS process. The LOCOS process also eliminates the poly stringer problem present in prior art structures by reducing the oxide step height. A transistor termination structure includes several field rings, each set of adjacent field rings separated by an insulated trench, thus allowing the field rings to be spaced very close together. The field rings and trenches are fabricated in the same steps as are corresponding portions of the active transistor.

Claims

1. A method for forming a field effect transistor comprising:

providing a semiconductor substrate having a principal surface and being of a first conductivity type;

forming a patterned mask layer on the principal surface;

doping semiconductor regions of a second conductivity type in the portions of the substrate exposed by the mask layer, thereby forming deep body regions of the transistor;

growing an oxide layer on the portions of the principal surface exposed by the mask layer;

forming a plurality of trenches in the substrate;

forming a layer of conductive material in the trenches and over at least a part of the oxide layer, the portion of the conductive material layer in the trenches being a gate of the transistor;

forming doped first regions of the second conductivity type in the substrate extending from the portions of the principal surface not covered by the oxide layer or the layer of conductive material into the substrate;

forming doped second regions of the first conductivity type extending from the unmasked portions of the principal surface into the substrate, the first and second doped regions respectively being body and source regions of the transistor;

forming a patterned insulating layer overlying the principal surface and the conductive material layer; and

forming a patterned interconnect layer overlying the principal surface and over the patterned

insulating layer and contacting the deep body, body,

and source regions, and the gate electrode.

2. The method of claim 1, wherein the step of growing an oxide layer comprises locally oxidizing the exposed portions of the principal surface to form a layer in the range of about 5,000 to about 8,000 Å

thick.

3. The method of claim 1, wherein the step of forming a plurality of trenches comprises:

anisotropically etching a plurality of U-shaped trenches;

smoothing the trench walls and rounding the trench corners by an isotropic plasma dry etch;

growing a layer of sacrificial oxide on the sidewalls of the trenches; and

removing at least part of the layer of sacrificial oxide.

4. The method of claim 3, wherein the step of forming the doped first regions is after the step of forming the plurality of trenches.

5. The method of claim 4, wherein the depth of the trenches is in the range of about 1.5 to about 3 microns.

6. The method of claim 1, wherein the step of forming a layer of conductive material comprises:

depositing a layer of material in the trenches and overlying the principal surface;

etching away a portion of the deposited layer;

doping remaining portions of the deposited layer;

forming a patterned mask layer over the doped deposited layer portions; and

etching away those portions of the doped deposited layer exposed by the patterned mask layer, wherein the trenches are filled with the doped deposited layer, and the doped deposited layer is over the oxide layer only in a termination region of the transistor.

7. The method of claim 6, wherein the step of forming a patterned interconnect layer comprises:

depositing a layer of metal overlying the principal surface and the patterned insulating layer;

forming a patterned mask layer over the layer of metal;

etching away those portions of the metal layer exposed by the patterned mask layer, and further etching away in the same step that portion of the doped deposited layer in the termination region that is not overlain by the patterned insulating layer.

8. A method for forming a field effect transistor comprising the steps of:

providing a semiconductor substrate having a principal surface and being of a first conductivity type;

forming a patterned mask layer on the principal surface;

forming a doped deep body region of a second conductivity type of the transistor in a portion of the substrate underlying the portions of the principal surface exposed by the patterned mask layer;

locally growing oxide on the principal surface at those portions of the principal surface exposed by the patterned mask layer;

removing the patterned mask layer, thereby exposing additional portions of the principal surface; and

forming in those portions of the substrate underlying the exposed additional portions of the principal surface a doped body region, a doped source region, and a gate region of the transistor.