Fixed-pattern noise correction circuitry for solid-state imager

• US 5,317,407 A
• Filed: 06/17/1992
• Issued: 05/31/1994
• Est. Priority Date: 03/11/1991
• Status: Expired due to Fees

• Current Assignee: General Dynamics Defense Systems Incorporated (General Dynamics Corporation)
• Original Assignee: General Electric Company
• Inventors: Michon, Gerald J.
• Primary Examiner(s): Razavi, Michael T.
• Assistant Examiner(s): Colaianni, Joseph
• Application Number:
  US07/900,504
• Time in Patent Office: 713 Days
• Field of Search: 358/213.18, 358/213.15, 358/213.11, 358/213.23, 358/213.13, 358/213.26, 358/213.31
• US Class Current: 348/306
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/67 applied to fixed-pattern noise, e.g. non-uniformity of response
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

An analog line store comprises a bank of storage capacitors n in number, an n:1 read multiplexer for sequentially sampling from the n storage capacitors as part of a read-then-write operation, a 1:n write multiplexer for sequentially sampling to the n storage capacitors as a further part of the read-then-write operation, and a scanning register for generating control signals for the write multiplexer and the read multiplexer. The storage capacitors have similar capacitances that are substantially invariant with change in stored charge. Such an analog line store is integrated together with a solid-state imager array to provide for the cancellation of fixed pattern noise from the imager video output signal.

Claims

1. A solid state imager including means for generating successive sequences of n analog samples supplied at a prescribed clocking rate, and a radiation tolerant analog delay line for delaying by n sample times those successive sequences of n analog samples supplied at a prescribed clocking rate, n being an integer at least fifty, said analog delay line comprising:

an input terminal for receiving said successive sequences of analog samples supplied at a prescribed clocking rate;

an output terminal for supplying said successive sequences of analog samples supplied at a prescribed clocking rate and delayed by n sample times;

a bank of linear storage capacitors, n in number, having similar capacitances that are substantially invariant with change in stored charge;

a 1;

n write multiplexer for sampling successive regularly clocked analog samples sequentially to said n storage capacitors for temporary storage therein, as latter parts of sequential read-then-write operations;

an n;

1 read multiplexer for sequentially sampling with substantially equal delays said temporarily stored analog samples from said n storage capacitors;

as earlier parts of sequential read-then-write operations; and

a scanner for generating control signals for said write multiplexer and said read multiplexer at said prescribed clocking rate, for implementing said sequential read-then-write operations.

2. The solid state imager as set forth in claim 1 wherein said means for generating successive sequences of n analog samples supplied at a prescribed clocking rate comprises:

a solid-state imager sequentially providing at a row scan rate pairs of concurrently generated lines of successive video samples, said successive samples in one line in each pair being generated by scanning a row of sensing elements before they are erased and said successive samples in the other line in that pair being concurrently generated by scanning a row of sensing elements after they are erased;

means for operating said solid-state imager for sequentially providing said successive video samples in each line at a pixel element scan rate corresponding to said prescribed clocking rate;

a first voltage amplifier for responding to the line of successive video samples generated by scanning a row of sensing elements before they are erased to generate first amplified samples; and

means for performing a correlated double sampling of said first amplified samples to generate first correlated double sampling results applied to the input terminal of said analog delay line as said successive sequences of analog samples supplied at a prescribed clocking rate.

3. The solid state imager as set forth in claim 1 disposed within the confines of a monolithic integrated circuit on an epitaxial layer of a first conductivity type silicon grown on a substrate of a second conductivity type silicon, which epitaxial layer is highly doped in certain regions thereof to form the first plates of said bank of storage capacitors and is largely overlain by an oxide layer, said oxide layer having disposed thereon a polysilicon layer selectively etched away, the second plates of said bank of storage capacitors being formed by remnant portions of said polysilicon layer.

4. The solid state imager as set forth in claim 1 wherein each said storage capacitor in said analog delay line has a respective first plate connected to a point of reference potential, has a respective second plate, and exhibits between its first and second plates a respective capacitance of prescribed value;

said combination further including;

a field effect transistor, having a gate electrode to which the output terminal of said analog delay line connects, and having a channel connected for supplying output signals linearly related to voltage between said point of reference potential and its gate electrode.

5. The solid state imager as set forth in claim 4 wherein said means for for supplying successive sequences of analog voltage samples comprises:

a solid-state imager sequentially providing at a row scan rate pairs of lines of successive video samples, one line generated by scanning a row of sensing elements before they are erased and the other line generated by scanning a row of sensing elements after they are erased;

means for operating said solid-state imager for sequentially providing said successive video samples in each line at a pixel element scan rate corresponding to said prescribed clocking rate;

a first voltage amplifier for responding to the line of successive video samples generated by scanning a row of sensing elements before they are erased to generate first amplified samples; and

means for performing a correlated double sampling of said first amplified samples to generate first correlated double sampling results applied to the input terminal of said analog delay line as said successive sequences of analog voltage samples supplied at a prescribed clocking rate.

6. The solid state imager as set forth in claim 5 further including:

means for differentially combining samples supplied to the output terminal of said analog delay line and samples supplied to a fixed-pattern-noise terminal, thereby to generate video signal substantially free of fixed pattern noise;

a second voltage amplifier for responding to the line of successive video samples generated by scanning a row of sensing elements after they are erased to generate second amplified samples, said second voltage amplifier and said second voltage amplifier having similar voltage gains;

means for performing a correlated double sampling of said second amplified samples to generate second correlated double sampling results;

a further storage capacitor, having a capacitance that is substantially invariant with change in stored charge;

a first switching device for sampling successive second correlated double sampling results to said further storage capacitor as a latter part of a further read-then-write operation;

a second switching device for sequentially sampling from said further storage capacitor to said fixed-pattern-noise terminal as an earlier part of said further read-then-write operation.

7. The solid state imager as set forth in claim 6 wherein said solid-state imager includes

a plurality of charge-injection devices arrayed by row and by column along row lines and column lines;

wherein said solid-state imager includes

a second scanner for sequentially selecting overlapping pairs of said row lines for reading from said solid-state imager respectively to said first voltage amplifier and to said second voltage amplifier;

wherein said solid-state imager includes

a third scanner for clamping to a direct potential the ones of said row lines not currently selected by said second scanner; and

wherein said means for operating said solid-state imager for sequentially providing said successive video samples in each line at a pixel element scan rate corresponding to said prescribed clocking rate includes said first scanner connected for sequentially selecting ones of said column lines.

9. A combination as set forth in claim 3 wherein said solid-state imager includes

a plurality of charge-injection devices arrayed by row and by column along row lines and column lines;

wherein said solid-state imager includes

a second scanner for sequentially selecting overlapping pairs of said row lines for concurrent reading from said solid-state imager respectively to said first voltage amplifier and to said second voltage amplifier;

wherein said solid-state imager includes

a third scanner for clamping to a direct potential the ones of said row lines not currently selected by said second scanner; and

wherein said means for operating said solid-state imager for sequentially providing said successive video samples in each line at a pixel element scan rate corresponding to said prescribed clocking rate includes said first scanner connected for sequentially selecting ones of said column lines.

8. A combination comprising:

a solid-state imager sequentially providing at a row scan rate pairs of concurrently generated lines of successive video samples, said successive samples in one line in each pair being generated by scanning a row of sensing elements before they are erased and said successive samples in the other line in that pair being concurrently generated by scanning a row of sensing elements after they are erased;

means for operating said solid-state imager for sequentially providing n said successive video samples in each line at a pixel element scan rate corresponding to a prescribed clocking rate, n being a plural number;

a first voltage amplifier for responding to the line of successive video samples generated by scanning a row of sensing elements before they are erased to generate first amplified samples;

means for performing a correlated double sampling of said first amplified samples to generate corresponding samples of first correlated double sampling results;

an analog delay line for delaying said samples of first correlated double sampling results by the time for one of said scannings of said rows of sensing elements, said analog delay line comprising

an input terminal for receiving said samples of first correlated double sampling results that are to be delayed,

an output terminal for supplying said samples of first correlated double sampling results that are delayed,

a bank n in number of storage capacitors having similar capacitances that are substantially invariant with change in stored charge,

a 1;

n write multiplexer for sampling said samples of first correlated double sampling results from said input terminal sequentially to said n storage capacitors as latter parts of sequential read-then-write operations,

an n;

1 read multiplexer for sequentially sampling as earlier parts of said sequential read-then-write operations said samples of first correlated double sampling results from said n storage capacitors to said output terminal as earlier parts of said sequential read-then-write operations, and

a first scanner for generating control signals for said write multiplexer and said read multiplexer at said prescribed clocking rate to implement said sequential read-then-write operations;

a second voltage amplifier for responding to the line of successive video samples generated by scanning a row of sensing elements after they are erased to generate second amplified samples, said first voltage amplifier and said second voltage amplifier having similar voltage gains;

means for performing a correlated double sampling of said second amplified samples to generate corresponding samples of second correlated double sampling results;

means for differentially combining samples supplied from the output terminal of said analog delay line and said corresponding samples of second correlated double sampling results, thereby to generate video signal substantially free of fixed pattern noise;

a further storage capacitor, having a capacitance that is substantially invariant with change in stored charge;

a first switching device for sampling successive second correlated double sampling results to said further storage capacitor as a latter part of a further read-then-write operation; and

a second switching device for sequentially sampling from said further storage capacitor to said fixed-pattern-noise terminal as an earlier part of said further read-then-write operation.

10. A semiconductor imager for use with first correlated double sampling apparatus, second correlated double sampling apparatus and differential combining apparatus;

said semiconductor imager comprising, within the confines of a single semiconductor die;

a first terminal for connecting to said first correlated double sampling apparatus;

a second terminal for connecting from said first correlated double sampling apparatus;

a third terminal for connecting to said second correlated double sampling apparatus;

a fourth terminal for connecting from said second correlated double sampling apparatus;

a fifth terminal for connecting to an input port of said differential combining apparatus;

a sixth terminal for connecting to another input port of said differential combining apparatus;

first and second voltage amplifiers having respective input ports, having respective output ports respectively connecting to said first terminal and to said third terminal, and exhibiting similar voltage gains;

a charge-injection-device imager having a plurality m times n in number of charge-injection devices, having an array of parallel row lines respectively identified in order of their appearance in said array thereof by consecutive ordinal numbers first through m^th, and having an array of parallel column lines respectively identified in order of their appearance in said array thereof by consecutive ordinal numbers first through n^th, m and n being positive integers not necessarily different from each other, said array of parallel column lines crossing said array of parallel row lines, and a respective one of said charge-injection devices being located at each said crossing;

a row scan generator for sequentially addressing successive overlapping pairs of adjacent ones of said first through m^th row lines for connection to respective ones of the input ports of said first and said second voltage amplifiers during read out from said charge-injection device imager, the addressing of each pair of row lines taking place during a respective row scan interval;

a column scan generator for sequentially addressing said first through n^th column lines during read out via said first and said second output lines from each sequentially addressed pair of adjacent ones of said first through m^th row lines, the addressing of each column line taking place during a respective column scan interval;

a clamp scan generator for clamping to fixed potential those row lines not addressed by said row scan generator during the current row scan interval;

a zeroeth capacitive storage device;

means for applying to said fifth terminal, during an earlier portion of each column scan interval, the potential across said zeroeth capacitive storage device, as a successive sample of said first signal;

means for charging said zeroeth capacitive storage device during a later portion of each column scan interval to the potential currently appearing at said second terminal;

a row of capacitive storage devices, n in number, respectively identified by consecutive ordinal numbers first through n^th, having respective first plates connected to receive a reference potential, having respective second plates, and exhibiting capacitances between their respective first and second plates that are similar to each other;

a read multiplexer responding to said column scan generator to apply to said sixth terminal, during an earlier portion of each column scan interval, the potential appearing on a successively scanned one of said first through N^th capacitive storage devices to said sixth terminal; and

a write multiplexer responding to said column scan generator to charge, during a later portion of each column scan interval, said successively scanned one of said first through N^th capacitive storage devices to the potential currently appearing at said fourth terminal.

11. A semiconductor imager as set forth in claim 10, wherein said read multiplexer comprises

a plurality of field-effect transistor switches, n in number, respectively identified by consecutive ordinal numbers first through n^th, each of said first through n^th field-effect transistor switches having a respective channel connecting between said fourth terminal and the second plate of the one of said row of capacitive storage devices identified by the same ordinal number as that field-effect transistor switch, each of said first through n^th field-effect transistor switches having a respective gate to which said column scan generator applies a switching signal;

and wherein said write multiplexer comprises

a plurality of field-effect transistor switches, n in number, respectively identified by consecutive ordinal numbers (n+1)^th through 2n^th, each of said (n+1)^th through 2n^th field-effect transistor switches having a respective channel connecting between said sixth terminal and the second plate of the one of said row of capacitive storage devices identified by the same ordinal number as that field-effect transistor switch, each of said first through n^th field-effect transistor switches having a respective gate to which said column scan generator applies a switching signal.

12. A semiconductor imager as set forth in claim 11 constructed to be tolerant of radiation;

wherein said charge-injection device imager is constructed on an N-type silicon epitaxial layer, wherein said field-effect transistor switches comprise p-channel metal-oxide-silicon insulated-gate field-effect transistors; and

wherein each said capacitive storage device uses as its first plate a heavily doped N+ top contact diffusion, uses as its second plate a heavily doped lower polysilicon layer also used for the gate electrodes of said field-effect transistor switches and uses as its dielectric a layer of oxide grown on the N+ top contact diffusion during the growth of oxide gate insulation for said field-effect transistor switches, thereby avoiding the use of oxide grown from a polysilicon layer as its dielectric.

13. A semiconductor imager as set forth in claim 10 in combination with first correlated double sampling apparatus, with second correlated double sampling apparatus, and with differential combining apparatus that generates image samples substantially free of fixed pattern noise.

14. A combination comprising:

a solid-state imager sequentially providing at a row scan rate pairs of concurrently generated lines of successive video samples, said successive samples in one line in each pair being generated by scanning at a prescribed clocking rate a row of sensing elements before they are erased, and said successive samples in the other line in that pair being concurrently generated by scanning at said prescribed clocking rate a row of sensing elements after they are erased;

a first voltage amplifier for responding to the line of successive video samples generated by scanning a row of sensing elements before they are erased to generate first amplified samples;

a second voltage amplifier for responding to the line of successive video samples generated by scanning a row of sensing elements after they are erased to generate second amplified samples, said first voltage amplifier and said second voltage amplifier having similar voltage gains;

an analog delay line having an input terminal for receiving a first stream of analog samples formed from said first amplified samples and having an output terminal for supplying a second stream of analog samples responding to said first stream of samples with delay equal to the time duration between successive ones of said scannings of rows of sensing elements; and

means for generating video signals with reduced fixed pattern noise by differentially combining with said second stream of analog samples a third stream of analog samples formed from said second amplified samples.

15. A combination as set forth in claim 14 including:

means for performing a correlated double sampling of said first amplified samples in forming said first stream of analog samples; and

means for performing a correlated double sampling of said second amplified samples in forming said third stream of analog samples.