Hybrid multiplex synchronizing method and apparatus therefor

• US 5,317,572 A
• Filed: 07/21/1992
• Issued: 05/31/1994
• Est. Priority Date: 07/23/1991
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Satoh, Junichi
• Primary Examiner(s): Chin, Wellington
• Application Number:
  US07/917,811
• Time in Patent Office: 679 Days
• Field of Search: 370/105.1, 370/105, 370/105.2, 370/108, 370/100.1, 370/105.4, 375/106, 375/111, 375/116, 375/114
• US Class Current: 370/509
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines
• CPC Class Codes: H04J 3/16 in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted H04J3/17, H04J3/24 take precedence

Abstract

Disclosed are a hybrid multiplex synchronizing method and apparatus therefor, in which, when time-shared multiplexed data having different frame patterns and different frame lengths are inputted in different phases every time slot, the data are transmitted upon making the phases of the data in each time slot identical. The apparatus stores in advance, in correlation with the time slots, types of frame patterns and frame lengths of time-shared multiplexed data allocated to each time slot, and performs frame-pattern detection processing in correspondence with each of the different frame patterns. A synchronized-phase detection signal is output in response to detection of the frame pattern, and when the synchronized-phase detection signal is generated in response to detection of the frame pattern of the time-shared multiplexed data allocated to each time slot, the time-shared multiplexed data in the each time slot is rearranged in memory, taking into consideration the frame length of these data, based upon the synchronized-phase detection signal. The phases of the data in each of the time slots are then identical to one another.

Claims

1. A hybrid multiplex synchronizing method in a data multiplex communication apparatus having multiplex synchronizing processors in which, when time-shared multiplexed data having prescribed frame patterns, some of which are different than others, are inputted in different phases every time slot, said multiplex synchronizing processors perform detection processing to detect frame patterns of time-shared multiplexed data allocated to said time slots and output synchronized-phase detection signals in response to detection of the frame patterns, and a phase synchronizer for rearranging the time-shared multiplexed data of each time slot in memory based upon the synchronized-phase detection signals and making the phases of the time-shared multiplexed data identical, said method comprising the steps of:

storing in advance, in correlation with time slots, information as to the types of frame patterns and frame lengths of time-shared multiplexed data allocated to each time slot, in a case where plural items of time-shared multiplexed data having different frame patterns and different frame lengths are processed;

providing multiplex synchronizing processors designated for respective ones of the frame patterns, performing frame-pattern detection processing in each of the multiplex synchronizing processors whenever a frame bit identifying one of the frame patterns is inputted, and outputting a synchronized-phase detection signal in response to detection of the frame pattern; and

when the synchronized-phase detection signal is generated by a multiplex synchronizing processor conforming to the type of frame pattern which corresponds to a present time slot, as determined from the stored information, having said phase synchronizer rearrange the time-shared multiplexed data in the present time slot in memory, upon taking into consideration the frame length of these data, based upon the synchronized-phase detection signal, and similarly rearrange the time-shared multiplexed data of each time slot in memory to make the phases of the time-shared multiplexed data of the time slots identical to one another.

2. The method according to claim 1, wherein the multiplex synchronizing data has a one-bit frame bit attached thereto and a frame pattern is composed of a string of said frame bits.

3. The method according to claim 1, comprising the step of providing one of said multiplex synchronizing processors with:

a memory for storing the latest (f-1)-number of frame bits in correlation with each time slot, where f represents frame length;

a mixer for outputting an f-bit frame pattern upon combining a newly inputted frame bit in the present time slot and said latest (f-1) -number of frame bits which correspond to the present time slot;

a comparator for comparing the combined frame pattern and a frame pattern set in advance, and outputting a synchronized-phase detection signal when the two compared patterns agree; and

a storing unit for storing the latest (f-1)-number of frame bits in said memory in correlation with the present time slot;

wherein the other multiplex synchronizing processors have solely a comparator and share the memory, mixer and storing unit provided in said one multiplex synchronizing processor.

4. The method according to claim 1, wherein said storing step is performed by providing memory having m-number of storage area which are first, second, . . . , m-th storage areas for every time slot, where m represents maximum frame length;

and

the following steps are performed in said phase synchronizer;

storing time-shared multiplexed data of frame length m allocated to a prescribed time slot in a first storage area conforming to said prescribed time slot in response to generation of the synchronized-phase detection signal, subsequently storing the time-shared multiplexed data of frame length m of said time slot in second, third, . . . , m-th storage areas successively until the synchronized-phase detection signal is generated, and storing the data from the first storage area again in response to generation of the synchronized-phase detection signal; and

storing time-shared multiplexed data of frame length k, where k represents the frame length of time-shared multiplexed data allocated to each time slot, and where k equals the actual frame length of a higher number so that m/k is an integer, of a prescribed time slot in the first storage area conforming to said time slot in response to generation of the synchronized-phase detection signal, subsequently storing the time-shared multiplexed data of frame length k in second, third, . . . , k-th storage areas successively, storing the data in a (k+1)th storage are conforming to said time slot in response to generation of the next synchronized-phase detection signal, subsequently storing the time-shared multiplexed data of said time slot in (k+2)th, (k+3)th, . . . , 2 k-th storage area successively, and thereafter similarly storing the data up to the m-th storage area and again storing the data from the first storage area in response to generation of the next synchronized-phase detection signal.

5. The method according to claim 4, wherein said phase synchronizer has an address generator for updating and outputting sub-rate addresses, which indicate the storage areas of said memory, every time slot;

wherein the time-shared multiplexed data of the present time slot is written in a storage area designated by the sub-rate address of the present time slot outputted from said address generator; and

when the time-shared multiplexed data have been written up to the m-th storage area every time slot, said address generator clears the sub-rate address of said time slot in response to generation of the next synchronized-phase detection signal.

6. The method according to claim 5, further comprising the steps of:

storing m/k in correlation with a time slot;

performing monitoring to determine whether m/k-number of the synchronized-phase detection signals have been generated with regard to said time slot;

incrementing the sub-rate address of said time slot in a case where m/k-number of the synchronized-phase detection signals have not been generated; and

clearing the sub-rate address of said time slot in a case where m/k-number of the synchronized-phase detection signals have been generated.

7. A hybrid multiplex synchronizing apparatus in which, when time-shared multiplexed data having prescribed frame patterns and different frame lengths, some of which are different than others, are inputted in different phases every time slot, the data are transmitted upon making the phases of the time-shared multiplexed data in each time slot identical, comprising:

a memory for storing in advance, in correlation with time slots, information as to the types of frame patterns and frame lengths of the time-shared multiplexed data allocated to each time slot;

multiplex synchronizing processes designated for respective ones of different frame patterns for performing, for every time slot, frame-pattern detection of the time-shared multiplexed data allocated to said time slot, and outputting a synchronized-phase detection signal in response to detection of the frame pattern;

a frame aligning RAM having m-number of storage areas which are first, second, . . . , m-th storage areas for every time slot, where m represents maximum frame length;

a selector for selecting and outputting the synchronized-phase detection signal generated by a multiplex synchronizing processor conforming to the type of frame pattern which corresponds to a present time slot, as determined from the information stored in said memory; and

a phase synchronizer which, on the basis of the synchronized-phase detection signal generated every time slot, stores the time-shared multiplexed data of each time slot in the corresponding m-number of storage areas of said frame aligning RAM in order, starting from the first storage area, upon taking into consideration the frame length, based upon the synchronized-phase detection signal, and makes the phases of the items of time-shared multiplexed data of the time slots identical to one another.

8. The apparatus according to claim 7, wherein one of said multiplex synchronizing processors includes:

a memory for storing the latest (f-1)-number of frame bits in correlation with each time slot, where f represents frame length;

a mixer for outputting an f-bit frame pattern upon combining a newly inputted frame bit in the present time slot and said latest (f-1)-number of frame bits which correspond to the present time slot;

a comparator for comparing the combined frame pattern and a frame pattern set in advance, and outputting a synchronized-phase detection signal when the two compared patterns agree; and

a storing unit for storing the latest (f-1)-number of frame bits in said memory in correlation with the present time slot;

wherein the other multiplex synchronizing processors have solely a comparator and share the memory, mixer and storing unit provided in said one multiplex synchronizing processor.

9. The apparatus according to claim 7, wherein said phase synchronizer:

stores time-shared multiplexed data of frame length m allocated to a prescribed time slot in a first storage area conforming to said time slot in response to generation of the synchronized-phase detection signal, subsequently stores the time-shared multiplexed data of frame length m of said time slot in second, third, . . . , m-th storage areas successively until the synchronized-phase detection signal is generated, and stores the data from the first storage area again in response to generation of the synchronized-phase detection signal; and

store time-shared multiplexed data of frame length k, where k represents the frame length of time-shared multiplexed data allocated to each time slot and where k equals the actual frame length or a higher number so that m/k is an integer, of a prescribed time slot in the first storage area conforming to said time slot in response to generation of the synchronized-phase detection signal, subsequently stores the time-shared multiplexed data of frame length k in second, third, . . . , k-th storage area successively, stores the data in a (k+1) th storage area conforming to said time slot in response to generation of the next synchronized-phase detection signal, subsequently stores the time-shared multiplexed data of said time slot in (k+2)th, (k+3)th, . . . , 2 k-th storage areas successively, and thereafter similarly stores the data up to the m-th storage area and again stores the data from the first storage area in response to generation of the next synchronized-phase detection signal.

10. The apparatus according to claim 9, wherein said phase synchronizer has an address generator for updating and outputting sub-rate addresses, which indicate the storage areas of said frame aligning RAM, every time slot;

wherein the time-shared multiplexed data of the present time slot is written in a storage area designated by the sub-rate address of the present time slot outputted from said address generator; and

after the time-shared multiplexed data have been written up to the m-th storage area every time slot, the sub-rate address of said time slot is cleared in response to generation of the synchronized-phased detection signal and the time-shared multiplexed data are stored from the first storage area.

11. The apparatus according to claim 10, wherein said phase synchronizer further comprises a memory for storing m/k in correlation with a particular time slot;

and

an address incrementing/clearing designating unit for performing monitoring to determine whether m/k-number of the synchronized-phase detection signals have been generated with regard to said time slot, inputting to the address generator a signal which designates incrementing of the sub-rate address of said time slot in a case where m/k-number of the synchronized-phase detection signals have not been generated, and inputting to the address generator a signal which designates clearing of the sub-rate address of said time slot in a case where m/k-number of the synchronized-phase detection signals have been generated.