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Method and apparatus for testing and configuring the width of portions of a memory

  • US 5,317,712 A
  • Filed: 12/19/1991
  • Issued: 05/31/1994
  • Est. Priority Date: 12/19/1991
  • Status: Expired due to Term
First Claim
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1. A circuit for testing and configuring a width of various portions of memory, comprising:

  • an address decoder for receiving an address presented on address lines coupled to said address decoder and for generating a memory control signal on an output line, a state of said memory control signal specifying a width of a portion of the memory corresponding to said address;

    a latch coupled to said output line for retaining the state of said memory control signal, said latch being activated when a valid address is presented on said address lines; and

    a control/test register coupled to said latch for receiving the state of said memory control signal retained by said latch, said control/test register being readable by a processor.

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