Method and apparatus for testing and configuring the width of portions of a memory
First Claim
1. A circuit for testing and configuring a width of various portions of memory, comprising:
- an address decoder for receiving an address presented on address lines coupled to said address decoder and for generating a memory control signal on an output line, a state of said memory control signal specifying a width of a portion of the memory corresponding to said address;
a latch coupled to said output line for retaining the state of said memory control signal, said latch being activated when a valid address is presented on said address lines; and
a control/test register coupled to said latch for receiving the state of said memory control signal retained by said latch, said control/test register being readable by a processor.
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Accused Products
Abstract
A circuit and a related process are utilized in a computer system for testing and configuring the width of various portions of memory in a memory array. The circuit captures a state of a memory width control signal (MEMCS16) during a test and configuration cycle, retains the state of the MEMCS16 signal for various blocks of memory, and controls the state of the MEMCS16 signal when a memory access to a particular memory block is made. The circuit tests the state of the MEMCS16 signal for various blocks of the system memory map and thereafter configures a memory control register appropriately. The state of the MEMCS16 signal is retained by a latch when a particular 128K region is accessed and a valid address is present on the address lines. The output of the latch is provided as a processor-readable test result in a bit of a control/test register.
12 Citations
14 Claims
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1. A circuit for testing and configuring a width of various portions of memory, comprising:
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an address decoder for receiving an address presented on address lines coupled to said address decoder and for generating a memory control signal on an output line, a state of said memory control signal specifying a width of a portion of the memory corresponding to said address; a latch coupled to said output line for retaining the state of said memory control signal, said latch being activated when a valid address is presented on said address lines; and a control/test register coupled to said latch for receiving the state of said memory control signal retained by said latch, said control/test register being readable by a processor. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A process for testing and configuring a width of various portions of a memory in a circuit having an address decoder for generating a memory control signal, a latch coupled to said address decoder for retaining a state of said memory control signal, and a control/test register coupled to said latch for receiving the state of said memory control signal retained by said latch, said control/test register being readable by a processor, said process comprising the steps of:
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providing an address and a memory width signal indicating a memory width to said address decoder, said memory width being the width of a corresponding portion of memory, said portion including a memory location specified by said address; latching said memory control signal generated by said address decoder, said latching step being performed by said latch when a valid address is provided to said address decoder; and reading the state of said memory control signal latched in said latching step. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A means for testing and configuring a width of various portions of a memory in a circuit having an address decoder for generating a memory control signal, a latch coupled to said address decoder for retaining a state of said memory control signal, and a control/test register coupled to said latch for receiving the state of said memory control signal retained by said latch, said control/test register being readable by a processor, said means for testing and configuring comprising:
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means for providing an address and a memory width signal indicating a memory width to said address decoder, said memory width being the width of a corresponding portion of memory, said portion including a memory location specified by said address; means for latching said memory control signal generated by said address decoder when a valid address is provided to said address decoder; and means for reading the state of said memory control signal latched by said means for latching.
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Specification