Digital sound source apparatus and external memory cartridge used therefor

• US 5,317,714 A
• Filed: 09/02/1991
• Issued: 05/31/1994
• Est. Priority Date: 01/26/1990
• Status: Expired due to Term

• Current Assignee: Nintendo Company Limited
• Original Assignee: Nintendo Company Limited
• Inventors: Nakagawa, Katsuya, Tanaka, Hideki, Yamato, Satoshi
• Primary Examiner(s): Robertson, David L.
• Application Number:
  US07/768,613
• Time in Patent Office: 1,002 Days
• Field of Search: 395/400, 395/425, 273/434, 273/435, 273/148 B, 273/DIG. 28
• US Class Current: 711/115
• CPC Class Codes: G11C 2207/16 Solid state audio deprecated, only for historical reasons, G06F3/16, G11B
• CPC Class Codes: G11C 27/00 Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

A digital sound source apparatus includes a semiconductor memory connected to a central processing unit. The memory has a quantized data storage area and a program data storage area. A quantized data train and a stop code are stored in a series of addresses in the quantized data storage area, a start address is set in a certain address in the program data storage area. When the start address is read from the program data storage area, the quantized data are sequentially read from the quantized data storage area and are sequentially loaded into a data register. When the stop code is read from the quantized data storage area, loading of the data into the data register is inhibited by a read/write control circuit, the quantized data loaded into the data register are converted into an analog sound signal by a D/A conversion circuit.

Claims

1. A digital sound source apparatus comprising:

a central processing unit for processing information in a digital manner;

an address bus connected to said central processing unit;

a data bus connected to said central processing unit;

a semiconductor memory connected to said address bus and said data bus and having a data storage area for storing quantized data in a predetermined address space and a data storage area for storing program data for reading and controlling at least the quantized data in response to access from said central processing unit, said semiconductor memory storing a plurality of quantized data for generating a series of sounds as a quantized data train and a stop code in a last address of the quantized data train in said quantized data storage area, and start address data for designating a start address of the quantized data train in a certain address in said program data storage area;

temporary storing means connected to said data bus for temporarily and sequentially storing the quantized data applied from said data bus every time a write signal is applied;

detecting means connected to said address bus for detecting that the address data applied to said semiconductor memory from said central processing unit designates said quantized data storage area;

write control means connected to said data bus for generating said write signal in response to an output of said detecting means to apply the write signal to said temporary storing means and for stopping the generation of the write signal in response to detection of said stop code; and

digital/analog converting means for sequentially converting the quantized data temporarily stored in said temporary storing means into an analog signal.

2. A digital sound source apparatus according to claim 1, wherein said write control means includes stop code detecting means for detecting said stop code and further includes inhibiting means for applying an interrupt signal to said central processing unit in response to an output of said stop code detecting means to inhibit addressing of said quantized data storage area.

3. A digital sound source apparatus according to claim 2, wherein said semiconductor memory further stores image processing data for causing said central processing unit to execute arithmetic operation processing for displaying an image, and said central processing unit is switched to execution of the arithmetic operation processing for displaying an image on the basis of the image processing data in response to application of the interrupt signal from the inhibiting means of said write control means.

4. An external memory cartridge detachably connected to an information processing unit which comprises a central processing unit for processing information in a digital manner, a first address bus and a first data bus respectively connected to said central processing unit, and a connector connected to said first address bus and said first data bus, said external memory cartridge comprising:

a semiconductor memory having a data storage area for storing quantized data in a predetermined address space and a data storage area storing program data for reading and controlling at least the quantized data in response to access from said central processing unit, said semiconductor memory storing a plurality of quantized data for generating a series of sounds as a quantized data train and a stop code in a last address of the quantized data train in said quantized data storage area, and start address data for designating a start address of the quantized data train in a certain address in said program data storage area;

a printed circuit board attachable to or detachable from said connector, said printed circuit board being formed with a plurality of terminal portions which are connected to said first address bus and said first data bus when the external memory cartridge is inserted into the connector, and a second address bus and a second data bus for connecting said first address bus and said first data bus to said semiconductor memory through respective terminal portions;

temporary storing means mounted on said printed circuit board and connected to said second data bus for temporarily and sequentially storing the quatized data applied from said second data bus sequentially every time a write signal is applied;

detecting means connected to said second address bus for detecting that the address data applied to said semiconductor memory from said central processing unit designates said quantized data storage area;

write control means connected to said second data bus for applying said write signal to said temporary storing means in response to an output of said detecting means and for stopping generation of the write signal in response to detection of said stop code; and

digital/analog converting means for sequentially converting the quantized data temporarily stored in said temporary storing means into an analog signal and outputting the analog signal through said terminal portions on said printed circuit board.