Nitridation of titanium-tungsten interconnects

• US 5,318,924 A
• Filed: 01/22/1993
• Issued: 06/07/1994
• Est. Priority Date: 10/03/1991
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Lin, Jung, Turner, John E.
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US08/008,052
• Time in Patent Office: 501 Days
• Field of Search: 437/190, 437/192, 437/200, 437/195, 257/764
• US Class Current: 438/649
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365

Abstract

A method of forming interconnects for submicron integrated circuits that allows use of titanium-tungsten as the interconnect material. The inherent instability of titanium-tungsten to oxidation is addressed by a nitridation process that includes exposing the interconnect to an ambient containing nitrogen (NH₃) at an elevated temperature. Typically, the process is a rapid thermal anneal. A local interconnect may be formed, whereafter an insulating layer can be deposited at a high temperature without causing oxidation within the local interconnect that would adversely affect the resistivity of the material.

Claims

1. A method of providing a single-layer local interconnect within an integrated circuit comprising,

providing a semiconductor wafer having spaced apart first and second electrode regions,

forming a layer of titanium atop said semiconductor wafer,

heating said semiconductor wafer, whereby first surface portions of said titanium react to form a silicide and second surface portions of said titanium remain unreacted,

removing said second surface portions of said titanium, leaving said silicide,

depositing a titanium-tungsten layer on said semiconductor wafer such that said titanium-tungsten contacts said silicide,

patterning said titanium-tungsten layer such that a single-layer local interconnect is formed from said first electrode region to said second electrode region,

nitriding said patterned titanium-tungsten layer, including heating said patterned titanium-tungsten layer and exposing said patterned titanium-tungsten layer to an ambient containing ammonia, thereby forming a nitrided titanium-tungsten interconnect, and

depositing an insulator layer on said titanium-tungsten interconnect, whereby a single-layer local interconnect is formed.

2. The method of claim 1 wherein said step of nitriding includes rapid thermal annealing at a temperature in the range of 600°

C. to 900°

C.

3. The method of claim 2 wherein said step of nitriding includes directing said ambient containing ammonia to said titanium-tungsten layer at a flow rate in the range of 3-10 liters/min and for a period in the range of 30 to 90 seconds.

4. A method of forming a local interconnect in a semiconductor integrated circuit comprising,

providing a semiconductor wafer having a plurality of electrode regions thereon,

depositing a layer of titanium over said electrode regions,

forming a silicide on said electrode regions,

depositing an interconnect layer of titanium-tungsten on said semiconductor wafer, including depositing said interconnect layer directly onto said silicide,

patterning said interconnect layer, including leaving a single-layer local interconnect extending from a first electrode region to a second electrode region,

exposing said local interconnect to a heated ammonia-containing ambient, thereby forming at least a portion of said local interconnect into a nitrided titanium-tungsten local layer, and

coating said local interconnect with an insulating layer, said insulating layer being deposited directly onto said local interconnect.

5. The method of claim 4 wherein said step of exposing is a step of rapid thermal annealing said local interconnect in a flow of ammonia, said flow being free of gases other than ammonia.

6. The method of claim 4 wherein said step of patterning includes leaving said local interconnect along an electrical path from a first electrode region and atop a field oxide region of said semiconductor wafer to a second electrode region.

7. The method of claim 4 wherein said step of forming said silicide is a step of forming self-aligned titanium disilicide.

8. The method of claim 4 wherein said step of depositing said interconnect layer is a step of sputter depositing titanium-tungsten.