Method of fabricating an ion sensitive field effect transistor with a Ta.sub.2 O.sub.5 hydrogen ion sensing membrane

• US 5,319,226 A
• Filed: 03/05/1992
• Issued: 06/07/1994
• Est. Priority Date: 09/06/1991
• Status: Expired due to Fees

• Current Assignee: Dong-Jin Kim
• Original Assignee: Dong-Jin Kim
• Inventors: Kwon, Dae H., Sohn, Byung K.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): TSAI, H JEY
• Application Number:
  US07/846,363
• Time in Patent Office: 824 Days
• Field of Search: 437/235, 437/42, 437/247, 437/29, 257/253, 257/414
• US Class Current: 257/253
• CPC Class Codes: G01N 27/414 Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS

Abstract

A fabricating method of an ion sensitive field effect transistor (ISFET) with a Ta₂ O₅ hydrogen ion sensing membrane, which comprises the steps of forming Ta₂ O₅ film with a thickness of about 400 to 500 A by RF reactive sputtering on a Si₃ N₄ /SiO₂ gate dielectric layer of the pH-ISFET, and annealing the resultant film at about 375° to 450° C. in oxygen gas ambience for about one hour. In forming the Ta₂ O₅ film on the pH-ISFET, the Ta₂ O₅ film formed in the area except the gate region of the pH-ISFET is removed by a lift-off process utilizing a positive PR film. The Ta₂ O₅ gate pH-ISFET according to the present invention has higher sensitivity and more stable operation characteristics than those of the conventional pH-ISFET, while the productivity and stability thereof are greatly improved by effecting a whole wafer process.

Claims

1. A method of fabricating an ion sensitive field effect transistor with a Ta₂ O₅ hydrogen ion sensing membrane, comprising the steps of:

forming a Si₃ N₄ /SiO₂ dielectric layer over a gate region of said ion sensitive field effect transistor;

depositing a film of Ta₂ O₅ having a thickness of about 400 to 500 Å

on said Si₃ N₄ /SiO₂ dielectric layer on said ion sensitive field effect transistor; and

annealing the resultant film at a temperature of about 375°

to 450°

C. in oxygen gas ambience.

2. The method according to claim 1, wherein said film of Ta₂ O₅ is deposited by RF reactive sputtering.

3. The method according to claim 1, wherein said film of Ta₂ O₅ formed in the areas surrounding said gate region of said ion sensitive field effect transistor are removed by a lift-off process utilizing a positive photosensitive film during a formation of said film of Ta₂ O₅ on said ion sensitive field effect transistor with said Si₃ N₄ /SiO₂ gate dielectric layer.

8. The method according to claim 1, wherein the temperature of the annealing of approximately 400°

in a reactive oxygen gas ambience for approximately one hour.

4. An ion sensitive field-effect transistor, comprising:

a semiconductor substrate of a first conductivity type having first and second diffusion regions of a second conductivity type separated and spaced-apart by a gate region, said first and second diffusion regions respectively defining a source region and a drain region;

a dielectric layer positioned upon the surface of said semiconductor substrate covering said source region, said gate region and said drain region;

an ion sensitive membrane formed on the dielectric layer over said gate region, said ion sensitive membrane being a Ta₂ O₅ compound having a thickness of approximately 400-500 Å

; and

first and second metal layers formed in V-shape and positioned upon the dielectric layer over said source region and said drain region, each of said first and second metal layers having a base at a center of one of said source region and said drain region.

5. The ion sensitive field-effect transistors as claimed in claim 4, wherein said ion sensitive membrane is formed on the dielectric layer by RF reactive sputtering and annealing at a temperature in the range of 300°

to 900°

C. in a reactive oxygen gas ambience for approximately one hour.

6. The ion sensitive field-effect transistor as claimed in claim 5, wherein the range of temperature of the annealing is prefer to be of 375°

to 425°

C. in a reactive oxygen gas ambience for approximately one hour.

7. The ion sensitive field-effect transistor as claimed in claim 4, wherein said ion sensitive membrane is formed on the dielectric layer by RF reactive sputtering and annealing at a temperature in the range of 375°

to 400°

C. in a reactive oxygen gas ambience for approximately one hour.

9. The ion sensitive field-effect transistor as claimed in claim 4, wherein the temperature of the annealing is preferred to be of approximately 400°

C. in a reactive oxygen gas ambience for approximately one hour.

10. A method of fabricating an ion sensitive field effect transistor on a semiconductor substrate of a first conductivity type having first and second diffusion regions of a second conductivity type separated and spaced-apart by a gate region, said first and second diffusion regions respectively defining a source region and a drain region, comprising the steps of:

forming a dielectric layer over the surface of said semiconductor substrate covering said source region, said gate region and said drain region;

forming first and second metal layers in V-shape positioned upon the dielectric layer over said source region and said drain region, each of said first and second metal layers having a base at a center of one of said source region and said drain region;

depositing an ion sensitive layer of Ta₂ O₅ compound having a thickness of approximately 400-500 Å

on the dielectric layer over said gate region; and

annealing said ion sensitive layer of Ta₂ O₅ compound at a temperature in the range of 375°

to 425°

C. in a reactive gas ambience.

11. The method of fabricating an ion sensitive field effect transistor as claimed in claim 10, wherein said reactive gas ambience is oxygen.

12. The method of fabricating an ion sensitive field effect transistor as claimed in claim 10, wherein said ion sensitive layer is deposited by RF reactive sputtering.

13. The method of fabricating an ion sensitive field effect transistor as claimed in claim 10, wherein said ion sensitive layer is annealed in said reactive gas ambience for approximately one hour.

14. The method of fabricating an ion sensitive field effect transistor as claimed in claim 10, wherein the temperature of the annealing is approximately at 400°

C. in said reactive gas ambience of oxygen for approximately one hour.

15. A method of fabricating an ion sensitive field effect transistor on a semiconductor substrate of a first conductivity type having first and second diffusion regions of a second conductivity type separated and spaced-apart by a gate region, each of said first and second diffusion regions respectively defining a source region and a drain region, comprising the steps of:

forming an insulation layer over the surface of said semiconductor substrate covering said source region, said gate region and said drain region;

forming first and second metal layers in a V-shape, positioned upon the insulation layer over said source region and said drain region, each of said first and second metal layers having a base at a center of each of said source and drain regions, and a channel having two ends extending in opposite directions away from the center of each of said source and drain regions;

depositing a photoresist layer on the surface of said first and second metal layers, thereby exposing said gate region;

sputtering a film of Ta₂ O₅ having a thickness of approximately 400-500 Å

over the surface of said photoresist layer and said gate region in a first gas ambience; and

removing said photoresist layer, thereby exposing the film of Ta₂ O₅ having a thickness of approximately 400-500 Å

over said gate region; and

annealing said semiconductor substrate having said film of Ta₂ O₅ over the gate region in a second gas ambience.

16. The method of fabricating an ion sensitive field effect transistor as claimed in claim 15, wherein said first gas ambience comprises argon and oxygen and said second gas ambience comprises oxygen, and said film of Ta₂ O₅ is being annealed in said second gas ambience for approximately one hour.

17. The method of fabricating an ion sensitive field effect transistor as claimed in claim 15, wherein said film of Ta₂ O₅ is being annealed at a temperature range of approximately 375°

to 425°

C.

18. The method of fabricating an ion sensitive field effect transistor as claimed in claim 16, wherein said film of Ta₂ O₅ is being annealed at a temperature range of approximately 400°

C. in said second gas ambience of oxygen for approximately one hour.

19. An ion sensitive field effect transistor, comprising:

a semiconductor substrate of a first conductivity type having first and second diffusion regions of a second conductivity type separated and spaced-apart by a gate region, each of said first and second diffusion regions respectively defining a source region and a drain region;

an insulation layer disposed over the surface of said semiconductor substrate covering said source region, said gate region and said drain region;

first and second metal layers positioned upon the insulation layer over said source region and said drain region, each of said first and second metal layers having a base at a center of each of said source and drain regions, and a channel having two ends extending in opposite directions away from the center of each of said source and drain regions; and

an ion sensitive layer of Ta₂ O₅ having a thickness of approximately 400-500 Å

disposed on the insulation layer over the gate region, wherein said ion sensitive layer being disposed on said insulation layer over the gate region comprises the steps of;

depositing a photoresist layer on the surface of said first and second metal layers, thereby exposing said gate region;

sputtering said ion sensitive layer of Ta₂ O₅ having a thickness of approximately 400-500 Å

over the surface of said photoresist layer and said gate region in a first gas ambience of argon and oxygen; and

removing said photoresist layer, thereby exposing said ion sensitive layer of Ta₂ O₅ having a thickness of approximately 400-500 Å

over said gate region; and

annealing said semiconductor substrate having said ion sensitive layer of Ta₂ O₅ over the gate region in a second gas ambience of oxygen.

20. The ion sensitive field effect transistor as claimed in claim 19, wherein said ion sensitive layer of Ta₂ O₅ is annealed in said second gas ambience for approximately one hour at a temperature range of 375°

to 425°

C.