Parallel-to-serial converter

• US 5,319,369 A
• Filed: 07/19/1993
• Issued: 06/07/1994
• Est. Priority Date: 07/20/1992
• Status: Expired due to Fees

• Current Assignee: Orange S.A.
• Original Assignee: Orange S.A.
• Inventors: Chemarin, Alain, Majos, Jacques
• Primary Examiner(s): Young, Brian K.
• Application Number:
  US08/093,584
• Time in Patent Office: 323 Days
• Field of Search: 341/101, 341/61, 341/68, 328/15, 328/16, 307/271
• US Class Current: 341/101
• CPC Class Codes: H03K 5/26 the characteristic being duration, interval, position, frequency, or sequence
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00

Abstract

Typically, a parallel-to-serial converter comprises a parallel-to-parallel register and a parallel-to-serial register. According to the prior art, a first clock signal the transfer of incoming parallel data words to outputs of the parallel-to-parallel register whereas the loading of the parallel-to-parallel register is rhythmed by a second clock signal which is independent of the first clock signal. According to the invention, a local base time produces the second loading clock signal and two clock signals substantially in phase-opposition so that there is time dependence between these signals. A phase analyzing circuit derives a control signal for selecting one of the two clock signals which are in phase-opposition as a function of a phase shift between the incoming parallel data words and the first clock signal.

Claims

1. A parallel-to-serial converter receiving incoming data words each having M parallel bits from a digital processing device for converting them into serialized bits transmitted at a first frequency in a transmission medium, comprising

a time base receiving a clock signal at said first frequency and producing

(1)--a loading clock signal at a second frequency M times less than said first frequency to rhythm a loading of said incoming data words which are received and which are previously transferred to outputs of a parallel-to-parallel register in a parallel-to-serial register,

(2)--a first clock signal at said second frequency transmitted to said digital processing device to synchronize said digital processing device, and

(3)--two second clock signals at said second frequency and substantially in opposition of phase to each other, and

a phase analyzing means for analyzing the phase of said incoming data words compared to the phase of said first clock signal in order to select one of said two second clock signals according to whether said incoming data words and said first clock signal are approximately in phase and in opposition of phase, respectively, in a selected clock signal which rhythms a transfer of said incoming data words to said outputs of the parallel-to-parallel register.

2. The parallel-to-serial converter as claimed in claim 1, wherein one of said two second clock signals is substantially in phase lead with respect to said first clock signal.

3. The parallel-to-serial converter as claimed in claim 1, wherein loading times of said parallel-to-serial register determined by said loading clock signal occur periodically substantially after transfer times of said incoming data words determined by any one of the two second clock signals.

4. A parallel-to-serial converter receiving incoming data words each having M parallel bits from a digital processing device for converting them into serialized bits transmitted at a first frequency in a transmission medium, comprising

(a) a time base receiving a clock signal at said first frequency and producing

(1) a loading clock signal at a second frequency M times less than said first frequency to rhythm a loading of said incoming data words which are received and which are previously transferred to outputs of a parallel-to-parallel register in a parallel-to-serial register,

(2) a first clock signal at said second frequency transmitted to said digital processing device to synchronize said digital processing device, and

(3) two second clock signals at said second frequency and substantially in opposition of phase to each other, a first of said second clock signals being produced directly and a second of said second clock signals being produced through a logic inverter receiving said first of said second clock signals, and

(b) a phase analyzing means for analyzing the phase of said incoming data words compared to the phase of said first clock signal in order to select one of said two second clock signals according to whether said incoming data words and said first clock signal are approximately in phase and in opposition of phase, respectively, in a selected clock signal which rhythms a transfer of said incoming data words to said outputs of the parallel-to-parallel register.

5. A parallel-to-serial converter receiving incoming data words each having M parallel bits for a digital processing device for converting them into serialized bits transmitted at a first frequency in a transmission medium, comprising

(a) a time base receiving a clock signal at said first frequency and producing

(1) a loading clock signal at a second frequency M times less than said first frequency to rhythm a loading of said incoming data words which are received and which are previously transferred to outputs of a parallel-to-parallel register in a parallel-to-serial register,

(2) a first clock signal at said second frequency transmitted to said digital processing device to synchronize said digital processing device, and

(3) two second clock signals at said second frequency and substantially in opposition of phase to each other, and

(b) a phase analyzing means for analyzing the phase of said incoming data words compared to the phase of said first clock signal in order to select one of said two second clock signals according to whether said incoming data words and said first clock signal are approximately in phase and in opposition of phase, respectively, in a selected clock signal which rhythms a transfer of said incoming data words to said outputs of the parallel-to-parallel register, said phase analyzing means comprising

(1) several cascade-connected delay means imposing delays the sum of which defines a predetermined phase analysis duration, to delay one of predetermined of M bit signals relative to said M parallel bits in said incoming data words in several delayed signals, respectively, said analysis duration being less than a half-period of said clock signals at the second frequency,

(2) several sampling means for sampling said first clock signal in response to predetermined logic transitions in said one predetermined of the M bit signal and said delayed signals in order to produce several sampling signals respectively, and

(3) a logic means for generating as a function of two of said several sampling signals a control signal whose two logic states select said two second clock signals, respectively.

6. The parallel-to-serial converter as claimed in claim 5 comprising a switching means receiving said second clock signals through two respective inputs and receiving said control signal through a control input for applying one of said two second clock signals to the parallel-to-parallel register as a function of the logic state of said control signal into said selected clock signal.

7. The parallel-to-serial converter as claimed in claim 5 wherein said phase analyzing means further comprises several storing means connected between said several sampling means and said logic means for storing logic states of said sampling signals produced respectively by said several sampling means for a duration of transmission of one of said incoming data words.

8. The parallel-to-serial converter as claimed in claim 5 wherein

said two of the several sampling signals result from sampling of said first clock signal by said one of the predetermined M bit signals and a most delayed of said several delayed signals, and

said logic means comprises a first input means sensitive to one of said two of the several sampling signals and to a signal inverted with respect to the other of said two of the several sampling signals for generating an initial logic state of said control signal selecting one of said two second clock signals, and a second input means sensitive to the other of said two of the several sampling signals and to a signal inverted with respect to said one of said two of the several sampling signals for generating a second logic state of said control signal selecting the other of said two second clock signals.

9. The parallel-to-serial converter as claimed in claim 5 wherein said phase analyzing means further comprises a means for forcing the control signal into a forced signal at a given state selecting one of said two second clock signals during an initial operating stage of said parallel-to-serial converter, and

said one predetermined of the M bit signals is received through a control signal initiating means to initiate to a stable definitive state during said initial procedure said forced control signal independently of any phase jitter in said incoming data words less than a maximal phase jitter.

10. The parallel-to-serial converter as claimed in claim 9 wherein said maximal phase jitter is substantially equal to the difference between the half-period of said clock signals at the second frequency and said phase analysis duration.

11. The parallel-to-serial converter as claimed in claim 9, wherein said initiating means comprises first and second delay means connected in cascade receiving said one predetermined of the M bit signals to produce first and second delayed signals, respectively, and a means for selecting during said initial stage, successively said first delayed signal, then said second delayed signal, then said one predetermined of the M bit signals, and finally said first delayed signal, each of said first and second delay means imposing a delay substantially equal to said maximal phase jitter.

12. The parallel-to-serial converter as claimed in claim 5 wherein each of said several cascade-connected delay means comprises at least one flip-flop, flip-flops of said several cascade-connected delay means being connected in cascade and having clock inputs receiving alternately, one out of two, said clock signal at said first frequency and a signal complementary to the latter.