Phase locked loop synchronization system for use in data communications

• US 5,319,680 A
• Filed: 09/03/1991
• Issued: 06/07/1994
• Est. Priority Date: 09/03/1991
• Status: Expired due to Term

• Current Assignee: The Whitaker Corporation (Meggitt PLC)
• Original Assignee: The Whitaker Corporation (Meggitt PLC)
• Inventors: Port, Adrian G., Spackman, Charles D.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Bocure, Tesfaldet
• Application Number:
  US07/753,704
• Time in Patent Office: 1,008 Days
• Field of Search: 375/119, 375/120, 375/110, 328/155, 360/38.1, 360/39, 331/12, 331/18, 331/25, 331/1 R, 331/2, 307/231, 307/511, 307/514
• US Class Current: 375/375
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/354 Astable circuits
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/14 for assuring constant frequency when supply or correction voltages fail or are interrupted
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A clock generator uses coarse and fine phase locking to lock an internal clock signal to an intermittently received data signal. The clock generator uses separate coarse and fine phase locked loops (PLL'"'"'s). The respective voltage controlled oscillators (VCO'"'"'s) of the PLL'"'"'s are made from matched components and the coarse control signal is applied to both VCO'"'"'s. The fine PLL locks the output signal provided by the second PLL in phase to the received data signal. The oscillatory signal provided by the second PLL is the output clock signal of the system. The fine phase control signal is combined with the coarse frequency control signal to generate the control signal for the second VCO. The fine phase control signal is generated by comparing transitions in a non-return to zero (NRZ) encoded data signal to corresponding transitions in the output clock signal. Phase correction errors made due to missing transitions in the encoded data signal are compensated by one type of phase detector which retains the previous levels of the received data signals. Another type of phase detector gates the clock signal into the loop filter only when it is coincident with detected transitions in the received data signal.

Claims

1. Apparatus for generating a clock signal which is locked in phase to a received signal having intermittent transitions which are synchronous with a transmitting clock signal having a nominal frequency, said apparatus comprising:

a source of reference signal having a predetermined frequency which is approximately equal to the nominal frequency;

first variable frequency oscillator means responsive to a coarse control signal for producing an oscillatory output signal;

coarse control means coupled to said first variable frequency oscillator means and responsive to said reference signal and to said oscillatory output signal, for generating said coarse control signal to lock the frequency of said oscillatory output signal to the reference signal;

second variable frequency oscillator means, responsive to a frequency control signal for producing said clock signal; and

fine control means, coupled to said coarse control means and to said second variable frequency oscillator means and responsive to said received signal, for augmenting said coarse control signal to generate said frequency control signal to lock the frequency and phase of said clock signal to said received signal.

2. The apparatus of claim 1 wherein:

the combination of said first variable frequency oscillator means and said coarse control means is a phase locked loop (PLL) having a predetermined loop time constant; and

the combination of said second variable frequency oscillator means and said fine control means is a further PLL having a loop time constant significantly less than said predetermined time constant.

3. The apparatus of claim 1 wherein said fine control means includes:

phase detecting means for emitting pulses having a first polarity and a second polarity, opposite to the first polarity, when said clock signal leads and lags the transitions of said received signal, respectively;

correcting means for recognizing when a transition in the received signal has not occurred and for emitting a pulse of said second polarity to correct for one of said pulses of said first polarity which was emitted by said phase detecting means in response to the recognized missing transition in said received signal; and

means for combining the pulses emitted by said phase detecting means and said correcting means to augment said coarse control signal to generate the frequency control signal for said second variable frequency oscillator means.

4. The apparatus of claim 1 wherein said fine control means includes:

pulse generating means, responsive to said received signal for generating pulses coincident with the transitions of said received signal;

gating means, coupled to said second variable frequency oscillator means and responsive to said generating pulses for providing said clock signal as an output signal while said pulse is active and for providing a high impedance as said output signal otherwise; and

means, including a capacitor for accumulating the output signal of said gating means to generate a signal value which is used to augment said coarse control signal to generate the frequency control signal for said second variable frequency oscillator means.

5. The apparatus of claim 1 wherein the source of reference signal is transmitting clock signal generator which provides a transmitting clock signal for encoding data to be sent to a remote data processing device.

6. The apparatus of claim 1 wherein:

said first variable frequency oscillator means includes a first voltage controlled oscillator and said second variable frequency oscillator means includes a second voltage controlled oscillator;

said coarse control means includes;

frequency detector means, coupled to said first voltage controller oscillator for generating a frequency difference signal indicating a difference in frequency between the oscillatory signal of said first variable frequency oscillator means and said reference signal; and

loop filter means, coupled to said frequency detector means for integrating the frequency difference signal to generate said coarse control signal; and

said fine control means includes;

phase detector means for generating a phase difference signal indicating a difference in phase between said received signal and said clock signal;

second loop filter means, coupled to said phase detector means for integrating said phase difference signal to generate a phase control signal; and

means for combining said phase control signal with said coarse control signal to generate said frequency control signal.

7. The apparatus of claim 6 wherein said first and second voltage controlled oscillators are constructed from matched components and, in the absence of said received signal, said coarse control signal conditions said first and second voltage controlled oscillators to oscillate at substantially the same frequency.

8. The apparatus of claim 7 wherein said first and second voltage controlled oscillators are included on a single integrated circuit.

9. Apparatus for generating a clock signal which is locked in phase to a received data signal having intermittent transitions, comprising:

variable frequency oscillator means, responsive to a control signal, for producing said clock signal;

phase detector means including;

means responsive to said clock signal and to said received data signal for generating pulses of a first polarity and pulses of a second polarity, opposite to the first polarity, when transitions of said clock signal respectively lead and lag transitions of said received data signal in phase;

means for recognizing when a transition in said received data signal did not occur during a previous period of said clock signal and when a pulse of said first polarity was erroneously emitted; and

means, coupled to the means for recognizing, for generating a compensating pulse of said second polarity to compensate for the pulse of said first polarity which was erroneously emitted during said previous period of said clock signal; and

filter means for combining the pulses of the first and second polarity and the compensating pulses generated by said phase detector means to generate said control signal for said variable frequency oscillator means.

10. In a data communications system including first and second data processing systems each including a respective internal clock signal generator which provides a respective internal clock signal, and means, coupled to said clock signal generator for encoding data for transmission to the other one of said first and second data processing systems as a data signal, each of said first and second data processing systems further including apparatus for receiving the data signal transmitted by the other one of said first and second data processing systems said apparatus comprising:

first phase locked loop means responsive to said internal clock signal including means for generating a first control signal and first variable frequency oscillator means, responsive to the first control signal for generating a first output oscillatory signal which is locked in frequency to said internal clock signal; and

second phase locked loop means including;

second variable frequency oscillator means responsive to a second control signal for generating a second output oscillatory signal which is locked in frequency and phase to said received data signal;

phase control means, responsive to said second output oscillatory signal and to said received data signal for generating a phase between said second output oscillatory signal and said received data signal; and

means for adding said first control signal and said phase error signal to generate said second control signal for said second variable frequency oscillator means.