Device with host indication combination
DCFirst Claim
1. A device for combining indications relating to transfer of data blocks to a destination device, comprising:
- a buffer memory;
means, coupled to the buffer memory, for receiving the data blocks from a data source, each data block having an amount of data;
means, coupled to the buffer memory and the destination device, for transferring the data blocks, including a first data block and second data block, from the buffer memory to the destination device;
means, coupled to the buffer memory and the destination device, for generating a first signal near the end of the transfer of the first data clock;
means, coupled to the buffer memory and the destination device, for generating a second signal near the start of the transfer of the second data block; and
means, coupled to the means for generating a first signal and the means for generating a second signal, for delaying the first signal for a time interval based upon an expected occurrence of the second signal.
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Abstract
Combined indication signals of data block transfers are generated by a device which reduces the number of interrupts to a host processor. The reduction in the number of interrupts enhances host system performance during data block transfers. An embodiment of the device may be a network adapter comprising network interface logic for transferring a data frame between a network and a buffer memory and host interface logic for transferring a data frame between a buffer memory and a host system. The network adapter further includes threshold logic for generating an early receive indication signal when a portion of the data frame is received. Indication combination logic delays the generation of a transfer complete interrupt to slightly before the expected occurrence of the early receive indication. The host processor is able to service both the transfer complete indication and the early receive indication in a single interrupt service routine caused by the transfer complete indication.
40 Citations
28 Claims
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1. A device for combining indications relating to transfer of data blocks to a destination device, comprising:
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a buffer memory; means, coupled to the buffer memory, for receiving the data blocks from a data source, each data block having an amount of data; means, coupled to the buffer memory and the destination device, for transferring the data blocks, including a first data block and second data block, from the buffer memory to the destination device; means, coupled to the buffer memory and the destination device, for generating a first signal near the end of the transfer of the first data clock; means, coupled to the buffer memory and the destination device, for generating a second signal near the start of the transfer of the second data block; and means, coupled to the means for generating a first signal and the means for generating a second signal, for delaying the first signal for a time interval based upon an expected occurrence of the second signal. - View Dependent Claims (2, 3, 4, 5)
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6. An apparatus for transferring data frames from a network transceiver, coupled with a network, to a host system, comprising:
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a buffer memory for storing a data frame; network interface logic, coupled to the buffer memory and the network transceiver, for transferring a data frame from the network transceiver to the buffer memory; receive threshold logic, coupled to the network interface logic, for generating an early receive indication signal responsive to transferring a portion of the data frame from the network transceiver to the buffer memory; host interface logic, coupled to the buffer memory and the host system, for transferring a data frame from the buffer memory to the host system; transfer complete logic, coupled to the host interface logic, for generating a transfer complete indication signal responsive to transferring a data frame to the host system; and indication combination logic, coupled to the receive threshold logic and the transfer complete logic, for delaying for a period of time the transfer complete indication signal. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. An apparatus for receiving a data frame from a network communication media, the apparatus coupled with the network communication media and a host system, the host system including a host processor with an interrupt service routine and host memory, the apparatus comprising:
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a buffer memory for storing a data frame; network interface logic, coupled to the communication media and the buffer memory, for transferring a data frame from the network communication media to the buffer memory; receive threshold logic, coupled to the network interface logic, for generating an early receive indication signal responsive to transferring a portion of the data frame to the buffer from the network communication media; host interface logic, coupled to the buffer memory and the host system, for transferring a data frame from the buffer memory to the host system; transfer complete logic, coupled to the host interface logic, for generating a transfer complete indication signal responsive to transferring a data frame to the host system from the buffer memory; control means, coupled to host interface logic and the host system, for generating an interrupt signal to the host processor responsive to the early receive signal or transfer complete indication signal and for posting status information representing the early receive and transfer complete indication signals which may be read by the host processor during the interrupt service routine; and indication combination logic, coupled to the receive threshold logic and the transfer complete logic, for delaying for a period of time the generation of the transfer complete indication signal. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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23. A network adapter, having a buffer memory, for transferring a data frame from a network transceiver, coupled with a network, to the buffer memory and transferring a data frame from the buffer memory to a host system including a host processor and host memory, the network adapter generating an interrupt signal to the host processor responsive to transferring a data frame, the host processor responding to the interrupt signal and servicing the network adapter during a period of time, the network adapter comprising:
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network interface logic, coupled to the buffer memory and the network transceiver, for transferring a data frame from the network transceiver to the buffer memory; receive threshold logic, coupled to the buffer memory and the network interface logic, for generating an early receive indication signal responsive to transferring the data frame from the network transceiver to the buffer memory, wherein the receive threshold logic includes; a counter, having a counter output and coupled to the buffer memory, for counting a portion of the data frame transferred to the buffer memory from the network transceiver; a first alterable storage location containing a receive threshold value; and
,means for comparing the counter output to the receive threshold value in the first alterable storage location and generating an indication signal responsive to a comparison to the counter output and the receive threshold value; host interface logic, coupled to the buffer memory and the host system, for transferring a data frame from the buffer memory to the host system; transfer complete logic, coupled to the host interface logic, for generating a transfer complete indication signal responsive to transferring a data frame to the host system; control means, coupled to the host interface logic, for generating an interrupt signal to the host processor responsive to the transfer complete indication signal and posting status information representing the early receive indication signal and transfer complete indication signal which may be read by the host processor; and indication combination logic, coupled to the receive threshold logic and the transfer complete logic, for delaying the transfer complete indication signal such that the early receive indication occurs during the period of time the host processor is servicing the network adapter. - View Dependent Claims (24, 25, 26, 27, 28)
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Specification