Device with host indication combination

• US 5,319,752 A
• Filed: 09/18/1992
• Issued: 06/07/1994
• Est. Priority Date: 09/18/1992
• Status: Expired due to Term

• Current Assignee: U.S. Ethernet Innovations
• Original Assignee: 3Com Corporation (HP Inc.)
• Inventors: Petersen, Brian, Lo, Lai-Chin
• Primary Examiner(s): Shaw, Dale M.
• Assistant Examiner(s): Meky, Moustafa M.
• Application Number:
  US07/947,773
• Time in Patent Office: 627 Days
• Field of Search: 395/200, 395/250, 364/239.4, 364/251.3, 364/938.2, 370/13.1, 370/17, 370/82, 370/83, 371/5.3, 371/20.1, 371/20.4, 371/22.1, 371/24, 371/37.9, 371/67.1, 371/71
• US Class Current: 709/234
• CPC Class Codes: G06F 13/128 for dedicated transfers to a network for protocol converters G06F13/387
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9047 including multiple buffers, e.g. buffer pools
• CPC Class Codes: H04L 49/9068 in the network interface card

Abstract

Combined indication signals of data block transfers are generated by a device which reduces the number of interrupts to a host processor. The reduction in the number of interrupts enhances host system performance during data block transfers. An embodiment of the device may be a network adapter comprising network interface logic for transferring a data frame between a network and a buffer memory and host interface logic for transferring a data frame between a buffer memory and a host system. The network adapter further includes threshold logic for generating an early receive indication signal when a portion of the data frame is received. Indication combination logic delays the generation of a transfer complete interrupt to slightly before the expected occurrence of the early receive indication. The host processor is able to service both the transfer complete indication and the early receive indication in a single interrupt service routine caused by the transfer complete indication.

Claims

1. A device for combining indications relating to transfer of data blocks to a destination device, comprising:

a buffer memory;

means, coupled to the buffer memory, for receiving the data blocks from a data source, each data block having an amount of data;

means, coupled to the buffer memory and the destination device, for transferring the data blocks, including a first data block and second data block, from the buffer memory to the destination device;

means, coupled to the buffer memory and the destination device, for generating a first signal near the end of the transfer of the first data clock;

means, coupled to the buffer memory and the destination device, for generating a second signal near the start of the transfer of the second data block; and

means, coupled to the means for generating a first signal and the means for generating a second signal, for delaying the first signal for a time interval based upon an expected occurrence of the second signal.

2. The device of claim 1, wherein the device is coupled to a host system and further comprising means for transferring the data blocks includes:

control means, coupled to the means for generating the first signal, for generating an interrupt signal responsive to the first signal and for supplying status information concerning the first and second data blocks which may be sued by the host system.

3. The device of claim 2, wherein the status information includes the first signal and the second signal.

4. The device of claim 1, wherein the means for generating the second signal includes:

a counter, having a counter output and coupled to the buffer memory, for counting the amount of data received by the buffer memory;

a first alterable storage location containing a ready threshold value;

means for comparing the counter output to the ready threshold value in the first alterable storage location and generating the second signal responsive to a comparison of the counter output and the ready threshold value.

5. The device of claim 4, wherein the means for delaying the first signal includes:

a second alterable storage location containing a transfer complete delay threshold value;

an adder, having an adder output and coupled to the counter and the second alterable storage location, for outputting the sum of the values of the counter output and the transfer complete delay threshold value; and

a comparator, coupled to the adder output and the first alterable storage location, for indicating the expected occurrence of the second signal responsive to a comparison of the adder output and the ready threshold value.

6. An apparatus for transferring data frames from a network transceiver, coupled with a network, to a host system, comprising:

a buffer memory for storing a data frame;

network interface logic, coupled to the buffer memory and the network transceiver, for transferring a data frame from the network transceiver to the buffer memory;

receive threshold logic, coupled to the network interface logic, for generating an early receive indication signal responsive to transferring a portion of the data frame from the network transceiver to the buffer memory;

host interface logic, coupled to the buffer memory and the host system, for transferring a data frame from the buffer memory to the host system;

transfer complete logic, coupled to the host interface logic, for generating a transfer complete indication signal responsive to transferring a data frame to the host system; and

indication combination logic, coupled to the receive threshold logic and the transfer complete logic, for delaying for a period of time the transfer complete indication signal.

7. The apparatus of claim 6, wherein the network interface logic waits an interframe spacing time interval between transferring successive data frames and the period of time occurs during the inter-frame spacing time interval.

8. The apparatus of claim 6, wherein the host interface logic includes:

transfer descriptor logic for mapping transfer descriptors from the host system to the buffer memory, the transfer descriptors identifying locations in host memory to which a data frame in the buffer memory is to be stored; and

upload logic, responsive to transfer descriptors in the buffer memory, for transferring a data frame from the buffer memory to host memory.

9. The apparatus of claim 6, wherein the host interface logic includes:

control means for generating an interrupt signal to the host system responsive to the transfer complete indication signal and for supplying status information which may be used by the host system.

10. The apparatus of claim 6, wherein the host system includes host address space, and the buffer memory comprises a buffer independent of the host address space.

11. The apparatus of claim 6, wherein the receive threshold logic includes:

a counter, having a counter output and coupled to the buffer memory, for counting the portion of the data frame transferred to the buffer memory from the network transceiver;

a first alterable storage location containing a receive threshold value;

means for comparing the counter output to the receive threshold value in the first alterable storage location and generating an early receive indication signal responsive to a comparison of the counter output and the receive threshold value.

12. The apparatus of claim 11, wherein the data frame includes a header field, including a destination address, followed by a data field and the receive threshold value is a look-ahead threshold value representing an amount of data relative to the beginning of the header field.

13. The apparatus of claim 12, wherein the network interface logic transfers the destination address from the network transceiver to the buffer memory during the period of time.

14. The apparatus of claim 12, wherein the network interface logic transfers the look-ahead threshold amount of data from the network transceiver to the buffer memory during the period of time.

15. The apparatus of claim 11, wherein the indication combination logic includes:

a second alterable storage location containing a transfer complete delay threshold value;

an adder, having an adder output coupled to the counter and the second alterable storage location, for outputting the sum of the values of the counter output and the transfer complete delay threshold value; and

a comparator, coupled to the adder output and the first alterable storage location, for indicating an end of the period of time responsive to a comparison of the adder output and the look-ahead threshold value.

16. An apparatus for receiving a data frame from a network communication media, the apparatus coupled with the network communication media and a host system, the host system including a host processor with an interrupt service routine and host memory, the apparatus comprising:

a buffer memory for storing a data frame;

network interface logic, coupled to the communication media and the buffer memory, for transferring a data frame from the network communication media to the buffer memory;

receive threshold logic, coupled to the network interface logic, for generating an early receive indication signal responsive to transferring a portion of the data frame to the buffer from the network communication media;

host interface logic, coupled to the buffer memory and the host system, for transferring a data frame from the buffer memory to the host system;

transfer complete logic, coupled to the host interface logic, for generating a transfer complete indication signal responsive to transferring a data frame to the host system from the buffer memory;

control means, coupled to host interface logic and the host system, for generating an interrupt signal to the host processor responsive to the early receive signal or transfer complete indication signal and for posting status information representing the early receive and transfer complete indication signals which may be read by the host processor during the interrupt service routine; and

indication combination logic, coupled to the receive threshold logic and the transfer complete logic, for delaying for a period of time the generation of the transfer complete indication signal.

17. The apparatus of claim 16, wherein the receive threshold logic includes:

a counter, having a counter output and coupled to the buffer memory, for counting the portion of the data frame transferred to the buffer memory from the network communication media;

a first alterable storage location containing a receive threshold value; and

means for comparing the counter output to the receive threshold value in the first alterable storage location and generating an indication signal responsive to a comparison to the counter output and the receive threshold value.

18. The apparatus of claim 17, wherein the data frame includes a header field, including a destination address, followed by a data field and the receive threshold value is a look-ahead threshold value representing an amount of data relative to the beginning of the header field.

19. The apparatus of claim 18, wherein there is an inter-frame spacing time interval between data frames transferred by the network interface logic and the period of time is during the inter-frame spacing time.

20. The apparatus of claim 18, the network interface logic transfers the destination address from the network transceiver to the buffer during the period of time.

21. The apparatus of claim 18, wherein the network interface logic transfers the look-ahead threshold amount of data from the network transceiver to the buffer during the period of time.

22. The apparatus of claim 17, wherein the indication combination logic includes:

a second alterable storage location containing a transfer complete delay threshold value;

an adder, having an adder output and coupled to the counter and the second alterable storage location, for outputting the sum of the values of the counter output and the transfer complete delay threshold value; and

a comparator, coupled to the adder output and the first alterable storage location, for indicating an end of the period of time responsive to a comparison of the adder output and the look-ahead threshold value.

23. A network adapter, having a buffer memory, for transferring a data frame from a network transceiver, coupled with a network, to the buffer memory and transferring a data frame from the buffer memory to a host system including a host processor and host memory, the network adapter generating an interrupt signal to the host processor responsive to transferring a data frame, the host processor responding to the interrupt signal and servicing the network adapter during a period of time, the network adapter comprising:

network interface logic, coupled to the buffer memory and the network transceiver, for transferring a data frame from the network transceiver to the buffer memory;

receive threshold logic, coupled to the buffer memory and the network interface logic, for generating an early receive indication signal responsive to transferring the data frame from the network transceiver to the buffer memory, wherein the receive threshold logic includes;

a counter, having a counter output and coupled to the buffer memory, for counting a portion of the data frame transferred to the buffer memory from the network transceiver;

a first alterable storage location containing a receive threshold value; and

,

means for comparing the counter output to the receive threshold value in the first alterable storage location and generating an indication signal responsive to a comparison to the counter output and the receive threshold value;

host interface logic, coupled to the buffer memory and the host system, for transferring a data frame from the buffer memory to the host system;

transfer complete logic, coupled to the host interface logic, for generating a transfer complete indication signal responsive to transferring a data frame to the host system;

control means, coupled to the host interface logic, for generating an interrupt signal to the host processor responsive to the transfer complete indication signal and posting status information representing the early receive indication signal and transfer complete indication signal which may be read by the host processor; and

indication combination logic, coupled to the receive threshold logic and the transfer complete logic, for delaying the transfer complete indication signal such that the early receive indication occurs during the period of time the host processor is servicing the network adapter.

24. The network adapter of claim 23, wherein the data frame includes a header field, including a destination address, followed by a data field and the receive threshold value is a look-ahead threshold value representing an amount of data relative to the beginning of the header field.

25. The network adapter of claim 24, wherein the transfer complete indication signal is generated after the destination address is transferred from the network transceiver to the buffer memory.

26. The network adapter of claim 25, wherein the transfer complete indication signal is generated before the look-ahead threshold value of data is transferred from the network transceiver to the buffer memory.

27. The network adapter of claim 24, wherein the indication combination logic includes:

a second alterable storage location containing a transfer complete delay threshold value;

an adder, having an adder output and coupled to the counter and the second alterable storage location, for outputting the sum of the values of the counter output and the transfer complete delay threshold value; and

a comparator, coupled to the adder output and the first alterable storage location, for indicating the expected occurrence of the early receive indication signal responsive to a comparison of the adder output and the look-ahead threshold value.

28. The network adapter of claim 23, wherein the transfer complete indication signal is generated after the portion of the data frame is transferred from the network transceiver to the buffer memory.